Chapter3 BIOS Setup
26
User’s Manual
DMA Clock Frequency: This option sets the DMA controller clock.
DMA MEMR IOW Synchronous: If enabled, the DMA controller will assert MEMR# at the same time as
IOW#. If disabled, MEMR# will be asserted one clock after IOW#.
DMA 16 Bit Wait State Cycles: This option specifies the number of wait states in 16-bit DMA cycle.
DMA 8 Bit Wait State Cycles: This option specifies the number of wait states in 8-bit DMA cycle.
PCI to Host Read Prefetch: If enabled, all QWORD aligned burst reads from a PCI master addressed to
the North Bridge system memory will use prefetch. If disabled, memory read cycles from PCI to host are
allowed to complete before the PCI cycle is terminated and all burst read attempts will be disconnected on
the PCI bus.
PCI to Host Write Posting: If enabled, all QWORD aligned burst write from a PCI master addressed to
the North Bridge system memory will be posted. If disabled, memory write cycles from PCI to host are
allowed to complete before the PCI cycle is terminated and all burst write attempts will be disconnected on
the PCI bus.
Memory Hole at 15M-16M: This option is used to reserve the memory block 15M-16M for ISA adadpter
ROM.
C0000-C7FFF cacheable: This option allows you to control the cacheability of C0000-C7FFF address.
SDRAM Clock: This option let you set the clock frequency of the SDRAM.
SDRAM Write Posting: This option controls the ability of SDRAM write posting.
Summary of Contents for IAC-H488 Series
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