background image

 

Smart Socket 

 

User Guide 

© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 

www.latticesemi.com/legal

.  

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-UG-02046-1.1 

 

23 

Appendix A. Smart Socket Board Schematics 

The following are representative schematics of a Smart Socket board. The FTDI and voltage regulator portions are the same across various Smart Socket boards. 

Figure A.1. USB Programming Interface 

5

5

4

4

3

3

2

2

1

1

D

D

C

C

B

B

A

A

USB Connection

VCC18FT

+3.3V

+5V_USB

+3.3V

+3.3V

VCC18FT

+3.3V

+3.3V

+3.3V

+5V_USB [3]

+3.3V

[3]

TCK [4]
TDI [4]

TDO [4]

TMS [4]

DONEb [3]

PWR_EN [3]
PWR_ENQ [3]

Date:

Size

Schematic Rev

of

Sheet

Title

Lattice Semiconductor Applications

Email: techsupport@Latticesemi.com

Board Rev

Project

September 26, 2017

B

A

6

2

USB Programming Interface

XO2 Programming Board (PSSN-FT256-LCMXO2)

A

Date:

Size

Schematic Rev

of

Sheet

Title

Lattice Semiconductor Applications

Email: techsupport@Latticesemi.com

Board Rev

Project

September 26, 2017

B

A

6

2

USB Programming Interface

XO2 Programming Board (PSSN-FT256-LCMXO2)

A

Date:

Size

Schematic Rev

of

Sheet

Title

Lattice Semiconductor Applications

Email: techsupport@Latticesemi.com

Board Rev

Project

September 26, 2017

B

A

6

2

USB Programming Interface

XO2 Programming Board (PSSN-FT256-LCMXO2)

A

L2

Ferrite_bead

R10

0

R3

2.2k

BC3

PWREN

C1
10nF

AD4

BC2

BC7

C6
100nF

BC0

BC6

C10

100nF

C11

100nF

C12
100nF

BC1

U2

M93C46-WMN6TP

M93C46_SOIC8

CS

1

SK

2

DIN

3

DOUT

4

VCC

8

NC

7

ORG

6

GND

5

BC5

AC4

BC4

C3
4.7uF

C9

100nF

AC0
AC1

R2

100k

R5
10k

FTDI High-Speed USB

          FT2232H

FT2232HL

U1

VREGIN

50

VREGOUT

49

DM

7

DP

8

REF

6

RESET#

14

EECS

63

EECLK

62

EEDATA

61

OSCI

2

OSCO

3

TEST

13

ADBUS0

16

ADBUS1

17

ADBUS2

18

ADBUS3

19

V

P

H

Y

4

V

P

L

L

9

V

C

O

R

E

1

2

V

C

O

R

E

3

7

V

C

O

R

E

6

4

V

C

C

IO

2

0

V

C

C

IO

3

1

V

C

C

IO

4

2

V

C

C

IO

5

6

A

G

N

D

1

0

G

N

D

1

G

N

D

5

G

N

D

1

1

G

N

D

1

5

G

N

D

2

5

G

N

D

3

5

G

N

D

4

7

G

N

D

5

1

PWREN#

60

SUSPEND#

36

ADBUS4

21

ADBUS5

22

ADBUS6

23

ADBUS7

24

ACBUS0

26

ACBUS1

27

ACBUS2

28

ACBUS3

29

ACBUS4

30

ACBUS5

32

ACBUS6

33

ACBUS7

34

BDBUS0

38

BDBUS1

39

BDBUS2

40

BDBUS3

41

BDBUS4

43

BDBUS5

44

BDBUS6

45

BDBUS7

46

BCBUS0

48

BCBUS1

52

BCBUS2

53

BCBUS3

54

BCBUS4

55

BCBUS5

57

BCBUS6

58

BCBUS7

59

C16

18pF

BD5

C18

100nF

AC2

R44

0

C17
18pF

AC3

R6

2.2k

1

2

C15

100nF

AD5

C13

100nF

AC5

X1

12MHZ

1

3

2

4

AC6
AC7

C4

100nF

AD7

L1

Ferrite_bead

C7
3.3uF

C14

100nF

BD3

R4

12k

R9

0

BD1
BD2

J1

USB_MINI_B

TYPE_B

VCC

1

D-

2

D+

3

GND

5

NC

4

CASE

7

CASE

8

CASE

9

CASE

6

MH1

10

MH2

11

R43

0

BD0

R11

0

C5

100nF

R8

0

BD4

R1
0

C2

10nF

BD6

R7

0

C8
100nF

BD7

EESK

EEDATA

SHLD

EECS

Summary of Contents for Smart Socket

Page 1: ...Smart Socket User Guide FPGA UG 02046 Version 1 1 April 2018...

Page 2: ...PGA UG 02046 1 1 Contents 1 Introduction 4 2 Features 4 3 Block Diagram 5 4 Board Specifications 6 5 Software Requirements 7 5 1 Generic Programming 7 5 2 Specific Software Requirements for Certain De...

Page 3: ...12 Figure 5 15 ASC Socket Add External ASC Device 12 Figure 5 16 ASC Socket ASC File Load Menu 13 Figure 5 17 ASC Socket Operation Menu 14 Figure 5 18 Warning 14 Figure 5 19 ASC Socket Warning for Ma...

Page 4: ...or Smart Socket replaces the legacy Lattice Model 300 and its associated Socket Adapters Smart Socket uses the same JTAG based Lattice Diamond Programmer programming software that is used with Lattice...

Page 5: ...chX02 have parts with different core supply voltage requirements The Smart Socket board jumper J2 allows you to select between 1 2 V and 3 3 V core supply voltage The selected core supply voltage is i...

Page 6: ...lders The specifications and information herein are subject to change without notice 6 FPGA UG 02046 1 1 4 Board Specifications The outline dimension is the same for all Smart Socket boards The dimens...

Page 7: ...downloaded at http www latticesemi com en Products DesignSoftwareAndIP FPGAandLDS LatticeDiamond aspx Smart Socket works with the Lattice Diamond Programmer using only a USB cable Connect the cable f...

Page 8: ...hown in Figure 5 3 Some device families may not support the scan operation For details see the Software Requirements for Specific Device Families section Figure 5 3 Unable to Identify Device In such c...

Page 9: ...without notice FPGA UG 02046 1 1 9 4 Select the appropriate programming file by clicking the Browse button in the Programming Options section as shown in Figure 5 6 5 Click OK Figure 5 6 Programming O...

Page 10: ...ithout notice 10 FPGA UG 02046 1 1 Figure 5 10 shows that the programming of device is in progress Figure 5 10 Programming in Progress 8 When the programming of the device is completed the Status opti...

Page 11: ...ily Done LED indication is not supported 5 2 2 ECP5 Device Family Programming The programming of ECP5 device family follows steps similar to the process described in the Generic Programming section Wh...

Page 12: ...ames are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 12 FPGA UG 02046 1 1 Figure 5 14 ASC Socket Devi...

Page 13: ...mes are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02046 1 1 13 Figure 5 16 ASC Socket ASC F...

Page 14: ...or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 14 FPGA UG 02046 1 1 Figure 5 17 ASC Socket Operation Menu The warn...

Page 15: ...greyed out to prevent adding a new file as shown in Figure 5 20 Figure 5 20 ASC Socket Ready to Program Step 8 Program the ASC device through the MachXO2 device on the Smart Socket board by clicking t...

Page 16: ...amming Completed 5 2 4 iCE40 Device Family Programming To program the iCE40 device 1 Launch the Lattice Diamond Programmer software The scanning of the device fails because the Scan operation is suppo...

Page 17: ...ut notice FPGA UG 02046 1 1 17 Figure 5 24 iCE40 Family Device Family List 3 Select the programming file to program the iCE40 device by double clicking the Browse button under File Name as shown in Fi...

Page 18: ...disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein a...

Page 19: ...gramming To program the CrossLink Device 1 Launch the Lattice Diamond Programmer software The scanning of the device fails as the Scan operation is supported over JTAG interface only and the CrossLink...

Page 20: ...r respective holders The specifications and information herein are subject to change without notice 20 FPGA UG 02046 1 1 Figure 5 29 CrossLink Family Device Family List 3 Select the programming file t...

Page 21: ...cations and information herein are subject to change without notice FPGA UG 02046 1 1 21 Figure 5 31 CrossLink Family Program Icon 5 When the programming of the device is completed the Status option c...

Page 22: ...listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change...

Page 23: ...e Schematic Rev of Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Board Rev Project September 26 2017 B A 6 2 USB Programming Interface XO2 Programming Board PSSN FT2...

Page 24: ...pplications Email techsupport Latticesemi com Board Rev Project September 26 2017 B A 6 3 Voltage Regulator and LEDs XO2 Programming Board PSSN FT256 LCMXO2 A Date Size Schematic Rev of Sheet Title La...

Page 25: ...LK CCLK P6 PB9B PB10B PB13B P7 PB12A PB15A PB18A P8 PB16B PB20B PB23B PCLKC2_1 P9 PB19B PB23B PB29B R10 PB22A PB27A PB35A R11 PB25A PB30A PB38A SN R12 PB22C PB26A PB34A R13 PB25D PB30D PB38D R14 PB3D...

Page 26: ...PR10A PR14A PR17A DQ1 K14 PR10B PR14B PR17B DQ1 K15 PR9B PR13B PR16B DQS1N K16 PR10D PR14D PR17D L12 PR12D PR16D PR21D L13 PR11B PR15B PR18B DQ1 L14 PR12A PR16A PR21A DQ1 L15 PR11A PR15A PR18A DQ1 L1...

Page 27: ...mation herein are subject to change without notice FPGA UG 02046 1 1 27 Appendix B Debugging Check the following if the programming fails USB power supply ON OFF switch is turned ON to provide power t...

Page 28: ...or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 28 FPGA UG 02046 1 1 Ensure that the ON OFF switch is turned to the...

Page 29: ...f their respective holders The specifications and information herein are subject to change without notice FPGA UG 02046 1 1 29 Revision History Date Version Change Summary April 2018 1 1 Changed docum...

Page 30: ...7th Floor 111 SW 5th Avenue Portland OR 97204 USA T 503 268 8000 www latticesemi com...

Reviews: