MIPI D-PHY Bandwidth Matrix Table
User Guide
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FPGA-UG-02041-1.1
7.
MIPI Data Rate Calculation
This section shows the calculations of the maximum data rate that can be achieved on Lattice FPGA products. The
values are based on data sheet specification of DDRX2/X4/X8 with clock and data center-aligned. These are MIPI
Alliance Specification compliant with ±0.15 UI setup/hold window on the receiver at ≤1 Gbps and ±0.15 UI skew
window on the transmitter at ≤1 Gbps.
This section also provides the method of calculating the windows if higher data rate is desired. The window for higher
data rate does meet MIPI Alliance Specification, but can still be practical in the user’s implementation. Check the latest
data sheet on the maximum data rate each Lattice FPGA device family can achieve.
7.1.
FPGA Receiver Interface
7.1.1.
MachXO2/MachXO3L
Maximum MIPI compliance data rate calculation for MachXO2/MachXO3L:
Max (0.233, 0.287) = 0.15 x UI
UI = 0.287/0.15 = 1.913 ns
Max Data Rate = 1/UI = 1/1.913 = 523 Mbps (at 0.15 UI)
Setup Time
Hold Time
0.233
0.287
MachXO2 Data Sheet Rev. 3.3 at 756 Mbps
Generic DDRX4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered
t
SU
Input Data Setup Before CLK
MachXO2-640U,
MachXO2-1200/U and
larger devices,
bottom side only
t
HO
Input Data Hold After CLK
f
DATA
DDRX4 Serial Input Data
Speed
f
DDRX4
DDRX2 ECLK Frequency
f
SCLK
SCLK Frequency
0.233
0.287
756
378
95
—
—
—
—
—
0.219
0.287
630
315
79
—
—
—
—
—
0.198
0.344
524
262
66
—
—
—
—
—
Mbps
MHz
MHz
ns
ns
Figure 7.1. MachXO2/MachXO3L Maximum Data Rate
