MIPI D-PHY Bandwidth Matrix Table
User Guide
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FPGA-UG-02041-1.1
19
7.1.2.
LatticeECP3
Maximum MIPI compliance data rate calculation for LatticeECP3:
Max (0.321, 0.321) = 0.15 x UI
UI = 0.321/0.15 = 2.14 ns
Max Data Rate = 1/UI = 1/2.14 = 467 Mbps (at 0.15 UI)
Setup Time
Hold Time
0.321
0.321
LatticeECP3 Data Sheet Rev. 2.8EA at 800 Mbps
Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX2_RX.ECLK.Centered) Using PCLK Pin for Clock Input
t
SUGDDR
t
HOGDDR
Data Hold After CLK
f
MAX_GDDR
DDRX2 Clock Frequency
321
—
405
321
—
—
403
—
325
403
—
—
ps
MHz
ps
Data Setup Before CLK
ECP3-150EA
ECP3-150EA
ECP3-150EA
Left and Right Sides
t
SUGDDR
Data Setup Before CLK
t
HOGDDR
Data Hold After CLK
—
—
—
335
335
405
—
—
—
425
425
325
ps
ps
MHz
DDRX2 Clock Frequency
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
t
SUGDDR
t
HOGDDR
Data Hold After CLK
321
—
321
—
403
—
403
—
ps
ps
Data Setup Before CLK
ECP3-70EA/95EA
ECP3-70EA/95EA
f
MAX_DDR
t
SUGDDR
Data Setup Before CLK
t
HOGDDR
Data Hold After CLK
—
—
—
335
335
405
—
—
—
425
425
325
ps
ps
MHz
DDRX2 Clock Frequency
ECP3-35EA
ECP3-17EA
ECP3-17EA
f
MAX_GDDR
—
405
—
325
MHz
DDRX2 Clock Frequency
ECP3-17EA
f
MAX_GDDR
471
—
280
471
—
—
—
—
—
535
535
250
535
—
535
—
—
—
—
535
535
250
—
250
Figure 7.2. LatticeECP3 Maximum Data Rate