MIPI D-PHY Bandwidth Matrix Table
User Guide
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FPGA-UG-02041-1.1
21
7.1.4.
CrossLink Soft D-PHY
Maximum MIPI compliance data rate calculation for CrossLink:
1200 Mbps at V
ID
= 140 mv
900 Mbps at V
ID
=140 mv
600 Mbps at V
ID
=70 mv
CrossLink Data Sheet Rev. 1.4
Figure 7.4. CrossLink Maximum Data Rate
7.1.5.
t
SU
/t
HD
Valid Window at Higher Data Rate
For data rate higher than specified above, the t
SU
/t
HD
window may exceed the 0.15 UI specified in the MIPI Alliance
Specification.
To calculate the window, the following equation can be used:
t
SU
/t
HD
Window = max(t
SU
/t
HD
) / (1 / Data Rate)
For 800 Mbps, 1 / Data Rate = 1.25 ns.
The maximum data rate each device can support on the receiver is limited to the data rate supported with
IDDRX2/X4/X8 with center-aligned data. This is summarized in
Table 7.1. t
SU
/t
HD
Window for Higher Data Rate
Device Family
Max Data Rate
Tsu/Thd Window
MachXO2
756 Mbps
0.217 UI
MachXO3L
900 Mbps
0.285 UI
LatticeECP3
800 Mbps
0.257 UI
ECP5
800 Mbps
0.257 UI
ECP5-5G
800 Mbps
0.257 UI
CrossLink Soft D-PHY
1200 Mbps at V
ID
=140 mv
0.20 UI
General Purpose I/O MIPI D-PHY Rx with 1:8 or 1:16 Gearing
t
SU_GDDRX_MP
Input Data Set-Up Before CLK
900 Mb/s < Data Rate ≤
1.2 Gb/s &
V
ID
= 140 mV
0.200
—
UI
600 Mb/s < Data Rate
≤
900 Mb/s &
V
ID
= 140 mV
0.150
—
UI
Data Rate ≤ 600 Mb/s &
V
ID
= 70 mV
0.150
—
UI
t
HD_GDDRX_MP
Input Data Hold After CLK
900 Mb/s < Data Rate ≤
1.2 Gb/s &
V
ID
= 140 mV
0.200
—
UI
600 Mb/s < Data Rate ≤
900 Mb/s &
V
ID
= 140 mV
0.150
—
UI
Data Rate ≤ 600 Mb/s &
V
ID
= 70 mV
0.150
—
UI
f
MAX_GDDRX_MP
Frequency for ECLK
3
csfBGA81, ctfBGA80,
ckfBGA80, ucfBGA64
—
600
MHz
WLCSP36
—
500
MHz
