Appendix II
LE3000S
25
The digital nature of the process introduces quantization effect into the conversion. The ratio
does not change smoothly. It tracks the clock rate variations in a quantized fashion (small
incremental jumps). Proper design requires that the quantized ratio changes fall below the ear
sensitivity levels. Tracking the clock rates sets restrictions on the maximum tolerable ratio step
size and the manner in which the ratio tracks the clocks rates. Let us focus on the two extreme
cases for ratio tracking:
a. Steady clocks: The converter is adjusting the ratio up and down by a small amount
around the correct average ratio.
b. Fast "varispeed": The adjustment accuracy is reduced with fast varispeed affecting the
accuracy of ratio adjustment.
Technological limitations require careful consideration for optimizing both ratio step size and
the tracking mechanism. Psychoacoustic considerations (listening tests) and practical
limitations of varispeed should form the basis for proper performance criteria. Measuring
asynchronous sample rate converters may reveal some of these compromises.
While the input and output of theoretical converters measure identically, real converters
continuously track and adjust internal coefficients. Such ratio modulation appears on FFT
measurements as a "widening of the main lobe" of a sinusoidal test tone. The amount of
widening depends greatly on variables such as ratio step size, ratio tracking, FFT size and type
of FFT window used.
Common digital domain measurements (FFT based measurements) do not show the effects of
low levels of incoming jitter. A common indirect approach is based on measuring the THD plus
noise reduction at the output of a reference DAC (driven by full-scale high frequency tone).
While such a measurement does not quantify jitter, it yields (in principle) the desired end result.
Real world limitations of reference DAC performance set limits to such measurements (DAC
performance is typically lower at high amplitudes and frequencies). Model 3000S utilizes a high
Q (steep resonance) LC circuit for de-jittering incoming data. Further jitter reduction may be
achieved with a 1:1 sample rate conversion, using a low jitter crystal clock oscillator for the
output data clock.
Sample rate converter performance should be measured over the usable audio range. Poor
performance at high frequencies cannot be dismissed as inaudible noise. A typical justification
for high frequency performance degradation is based on the fact that real music contains less
energy at this frequency range. This could allow, at most, a few dB reduction in THD+N. Unlike
many unsampled analog circuits which tend to generate higher frequency distortions, sampling
folds back distortion energy to lower frequencies, including the ear’s most sensitive mid-range
region.
When processing long words a desirable performance specification should exceed the
limitations of a 16 bit word by a significant margin. This will ensure that overall performance is
limited almost completely by word length bottleneck. (Truncation of a long word to 16 bits
yields theoretical results of approximately 98 dB THD+N). The combination of long word format
and good performance specifications is even more desirable when additional processing may
take place. Premature truncation amounts to loss of detail.
Summary of Contents for 3000S
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