–
gggGB
is the total capacity, in gigabytes, for primary bus (ECC not counted) 4GB, 8GB, 16GB, etc. (no
space between digits and units)
–
pheR
is the number of package ranks of memory installed and number of logical ranks per package
rank
– p =
• 1 = 1 package rank of SDRAMs installed
• 2 = 2 package ranks of SDRAMs installed
• 3 = 3 package ranks of SDRAMs installed
• 4 = 4 package ranks of SDRAMs installed
– he = blank for monolithic DRAMs, else for modules using stacked DRAM:
• h = DRAM package type
–
D = multi-load DRAM stacking (DDP)
–
Q = multi-load DRAM stacking (QDP)
–
S = single load DRAM stacking (3DS)
• e = blank for SDP, DDP and QDP, else modules using 3DS stacks, logical ranks per package rank
–
2 = 2 logical ranks in each package rank
–
4 = 4 logical ranks in each package rank
–
8 = 8 logical ranks in each package rank
– R = rank(s)
– xff = Device organization (data bit width) of SDRAMs used on this assembly
• x4 = x4 organization (4 DQ lines per SDRAM)
• x8 = x8 organization
• x16 = x16 organization
–
wwwww
is the DIMM bandwidth, in MBps: 2133, 2400, 2666, 2933, 3200
–
aa
is the SDRAM speed grade
–
m
is the DIMM type
– E = Unbuffered DIMM (UDIMM), x64 p 8 bit ECC module data bus
– L = Load Reduced DIMM (LRDIMM), x64 p 8 bit ECC module data bus
– R = Registered DIMM (RDIMM), x64 p 8 bit ECC module data bus
– U = Unbuffered DIMM (UDIMM) with no ECC (x64-bit primary data bus)
–
cc
is the reference design file used for this design
–
d
is the revision number of the reference design used
–
bb
is the JEDEC SPD Revision Encoding and Additions level used on this DIMM
The following illustration shows the location of the DIMM connectors on the system board.
.
Hardware replacement procedures
75
Summary of Contents for ThinkAgile VX3720 7Y12
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