Lexicon RV-8 Service Manual Download

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RV-8 Service Manual

from the propagation delay of a gate within U7. The resultant signal

DELWE/

is the write enable for U19.

Software requirements dictate that the FLASH address space begin at 0x80000. U13 decodes out the
start address with chip select. When

CRY_A19

is high and

CRY_NVCS/

is low, pin 4 of U13 goes low.

This signal is used as the chip select for the FLASH,

CRY_FLCS/

Due to another bug within the CS49400, writing the FLASH must be accomplished by using GPIO20 and
GPIO21 as address pins. At the beginning of a write cycle to the FLASH, erase commands are sent to
specific addresses within the device.

GPIO[21:20]

take the place of

CRY_A[1:0]

during this phase of the

operation. During normal read operations, the GPIO pins are programmed to be always low, and

CRY_A[1:0]

are passed along to U19 via OR-gates U7. During read cycles,

DELWE/

is driven high while

the output enable signal

CRY_NVOE/

is driven low, enabling the read buffers on U19. All data transfers

are eight-bits wide, and are accomplished via data bus

CRY_D[7:0]

In future revisions of the CS49400 silicon, all delay and logic steering circuitry will be designed out.
Provision to remove the delay elements from the circuit is provided by R51, R52, R54, and R56.

Audio Output Port

Signals: DEC_MCKI, DEC_OUT_SCKI, DEC_OUT_FSI, DEC_SDO[3:0]

The Format Decoder outputs four I

S audio data streams to the AVRX FPGA,

DEC_SDO[3:0]

. These are

multiplexed to an eight channel serial interface that is in the Analog Devices SPORT mode. This eight
channel interface drives the SPORT inputs of the SHARCs. The serial bits are synchronous with

DEC_OUT_SCKI

, which is equal to 64 * FS.

DEC_OUT_FSI

is the audio output sample rate clock.

Output Port Map Table

Pin Number

Pin Name

Signal

Map

110 AUDATA0

DEC_SDO0

Left/Right

109 AUDATA1

DEC_SDO1

Center/Sub

107

AUDATA2

DEC_SDO2

Left Surround/Right Surround

106

AUDATA3

DEC_SDO3

Downmix OR Left Back/Right Back

DEC_MCKI

is the master serial bit clock for the Format Decoder, and is provided by the AVRX FPGA, as

are

DEC_OUT_SCKI

and

DEC_OUT_FSI

Test Pins

Signals: TEST, DBCK, DBDA, FDBDA, FDBCK

These pins are pulled up to +2.5V via RP8 for normal operation, with the exception of

TEST

, which is

pulled down. These pins are for internal testing by the manufacturer and serve no useful function to this
application.

Power Supply and Ground

Signals: +2.5VD, +3.3VD, DGND

The CS49400 operates with 3.3V I/O and a core voltage of 2.5V. There are seven core voltage pins tied
to +2.5VD by a mini-plane on the PCB and four I/O voltage pins tied to the system wide 3.3VD plane.
Diode D24 is a fast SCHOTTKY device rated with a forward current of 1A. The diode clamps the core
voltage supply pins to the I/O supply pins. This ensures that the I/O pins will track the core voltage at
power-up. Destruction of the chip could result if the I/O voltage rises faster than the core voltage. With
this topology, the 3.3VD supply will be pulled along with the 2.5VD supply if the 3.3V supply is slow in

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