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RV-8 Service Manual

FPGA Programming Source Configuration Table

FPGA PROGRAMMING CONFIGURATION

R128 R129 R130 R131 R133 R134 R135 R148 R149 R150 R15

1

R157 R158 MODE

IN

IN

IN

IN

OUT OUT OUT IN

OUT IN

OUT

OUT IN

Host
Programming
(Default)

OUT

OUT

OUT

OUT

IN IN IN OUT

IN OUT

IN

IN OUT

EPROM
Programming
(Development)

Host Bus Interface

Signals: CPUADDR[9:0], LVDATA[7:0], CPUCS2/, CPUWRL/, CPURD/, BUFDIR, CPUCLKOUT, RESET/

The AVRX FPGA internal registers are contained entirely within the CS2/ memory space of the host CPU.
Therefore, the memory space that these registers occupy begins at a base address of 0x00800000.
Register accesses are implemented over a byte wide data bus

LVDATA[7:0]

with 1Kbytes of addressing

implemented over a 10-bit wide address bus

CPUADDR[9:0]

. Write accesses are made when the host

CPU asserts

CPUWRL/

and

CPUCS2/

to low states. Read accesses are made when the host CPU

asserts

CPURD/

and

CPUCS2/

to a low state.

The FPGA has 5 volt tolerant IO, so the address, chip select, read and write control lines come directly
from the CPU. During read cycles, the FPGA places data on the bus at 3.3V logic levels. This must be
level shifted into the 5V domain to be reliably read by the CPU. The bi-directional ports on sheet two of
this schematic provides this level translation to and from the CPU. The direction of these level-shifting
transceivers is controlled by

BUFDIR

. This signal is low during write cycles to the FPGA, and high during

read cycles from the FPGA.

CPU accesses to and from the FPGA are synchronous with the core frequency of the host processor,
25MHz. This clock is provided by the host to the FPGA as CPUCLKOUT.

RESET/

is a power-up reset signal that clears the state of the internal registers to zero. This signal serves

little more purpose than to be a fail safe mechanism to ensure proper resetting of the FPGA, as this
device is cleared whenever the power to the unit is removed. The FPGA is re-configured at each power-
up and boot phase.

Interrupt Sources

Signals: WCLKDIV8INT/, LVKYBDIRQ/, LVDSPABIRQ/, LVCRYIRQ/, LVVIDTUNIRQ/

WCLKDIV8INT/

is an interrupt to the SHARC DSPs that occurs once every eight audio samples being

presented to the SPORT IO.

LVKYBDIRQ/

is an interrupt to the host CPU that is generated each time a button on the front panel is

pressed. A second interrupt is generated when the key is released. This carries a host interrupt priority of
level 0. This interrupt is level shifted to 5V prior to being presented to the CPU.

LVDSPABIRQ/

is an interrupt to the host CPU that is generated whenever a read or write transaction via

the SHARC SPI ports has been completed. This carries a host interrupt priority of level 2. This signal is
level shifted to 5V prior to being presented to the CPU. At present, this interrupt is masked off and unused
by system software.

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Summary of Contents for RV-8

Page 1: ...RV 8 Receiver Service Manual Harman Specialty Group 3 Oak Park Bedford MA 01730 1413 USA Customer Service Telephone 781 280 0300 Service Fax 781 280 0499 www lexicon com Part No 070 17537 Rev 0 ...

Page 2: ... as when a power supply cord or plug is damaged liquid has been spilled or objects have fallen into the apparatus the apparatus has been exposed to rain or moisture does not operate normally or has been dropped 15 Refer to the operating instructions for power requirements Be advised that different operating voltages may require the use of different line cord and or attachment plug 16 Do not instal...

Page 3: ...electrical instrument in such an environment constitutes a definite safety hazard KEEP AWAY FROM LIVE CIRCUITS Operating personnel must not remove unit covers Qualified maintenance personnel must make component replacements and internal adjustments Do not replace components with the power cord connected Under certain conditions dangerous voltages may exist even with the power cord removed To avoid...

Page 4: ...k Park Bedford MA 01730 1413 USA Telephone 781 280 0300 Fax 781 280 0490 www lexicon com Customer Service Telephone 781 280 0300 Sales Fax 781 280 0495 Service Fax 781 280 0499 WARNING These service instructions are only intended for use by qualified personnel Do not perform any servicing other than that contained in these instructions unless qualified to do so Refer to the Safety Summary on the p...

Page 5: ...Tests 4 22 Lexicon Audio Precision ATE Summary 4 29 CHAPTER 5 TROUBLESHOOTING 5 1 Diagnostic Categories 5 1 Power On Modes 5 1 Diagnostic User Interface 5 1 Diagnostic Reporting 5 2 Power On Diagnostics 5 6 Extended Diagnostics Tests 5 8 Functional Diagnostic Descriptions 5 11 Disassembly Instructions 5 19 CHAPTER 6 THEORY OF OPERATION 6 1 RV 8 Amplifier Theory 6 1 RV 8 Analog Board Theory 6 4 RV ...

Page 6: ...sembly 7 17 Video Out Board Assembly 7 17 Power Supply Board Subassembly 7 17 Chassis Assembly 7 18 FP Mechanical Assembly 7 20 Video Mechanical Assembly 7 20 Tuner Preamp Mechanical Assembly 7 20 Fan Assembly 7 21 Power Supply Mechanical Assembly 7 21 Bridge Rectifier Assembly 7 21 VCO Mechanical Assembly 7 21 3 Channel Amp Bd Mechanical Assembly 7 21 4 Channel Amp Bd Mechanical Assembly 7 21 Sin...

Page 7: ...ENT 080 15645 ASSY DWG ACCESS 080 15646 ASSY DWG CHASSIS 080 15647 ASSY DWG MECH FP 080 15648 ASSY DWG MECH VIDEO 080 15649 ASSY DWG FAN 60MM 080 15848 ASSY DWG MECH TUNER PREAMP 080 16434 ASSY DWG AMP 3CH 080 16435 ASSY DWG AMP 4CH 080 16436 ASSY DWG MECH PS 080 16437 ASSY DWG BRIDGE RECT 080 16438 ASSY DWG HS SGL 080 16439 ASSY DWG HS DBL SCHEMATICS 060 13699 SCHEM IR ENC BD 060 15509 SCHEM VIDE...

Page 8: ......

Page 9: ...3 5 digits 0 5 or better accuracy Low Distortion Audio Oscillator with single ended or balanced analog outputs switchable 30kHz low pass filter or band pass 20 20kHz filter and output THD N 001 Distortion Analyzer with switchable 30Hz high pass filter or band pass 20 20kHz filter Digital Distortion Analyzer RS232 DB9 wrap around plugs These are created by connecting pins 2 3 of a female DB9 connec...

Page 10: ...emote control Required Tools Clean antistatic well lit work area with grounding wrist strap Number 1 Phillips tip screwdriver magnetic tip preferred Number 2 Phillips tip screwdriver magnetic tip preferred 1 4 hex nut driver full hollow 7 16 hex nut driver full hollow 9 32 hex nut driver full hollow M8 slotted mini phone jack driver Slim needle nose pliers 9 32 7 16 1 4 and 3 16 sockets 1 8 drive ...

Page 11: ...s to HSG Lexicon for Service Before returning a unit for warranty or non warranty service consult with HSG Lexicon Customer Service to determine the extent of the problem and to obtain Return Authorization No equipment will be accepted without Return Authorization from HSG Lexicon If HSG Lexicon recommends that a RV 8 be returned for repair and you choose to return the unit to HSG Lexicon for serv...

Page 12: ... the name of the person at HSG Lexicon and give the name and daytime telephone number of the person directly responsible for maintaining the unit Do not include accessories such as manuals cables remote control etc with the unit unless specifically requested to do so by HSG Lexicon Customer Service personnel 2 2 ...

Page 13: ...and 1 optical connector Zone 3 Audio Output 1 Stereo RCA variable output level connector Headphone Output 1 Stereo 1 4 inch phone connector Amplifier Outputs 7 Channels 2 channels assignable to Zone 2 or Zone 3 Main Zone Audio Performance A D Conversion 24 bit 96kHz multi bit Σ architecture D A Conversion 24 bit 44 1 to 192kHz multi bit Σ architecture Frequency Response 20Hz to 20kHz 0 1dB 0 1dB 0...

Page 14: ...e Below 0 005 at 1kHz 1Vrms output level Dynamic Range 101dB minimum 22kHz bandwidth Signal to Noise Ratio 101dB minimum 22kHz bandwidth Input Sensitivity 200mVrms 4Vrms for maximum output level Input Impedance 100kΩ in parallel with 150pF Preamp Output Level 200mVrms typical 4Vrms maximum maximum value with full scale input signal and volume at 0dB Preamp Output Impedance 300Ω in parallel with 15...

Page 15: ...ive Impedance 75Ω Bandwidth 150MHz Insertion Loss 3dB Video Converter NTSC PAL SECAM to Y Pb Pr Other Trigger Outputs 1 Power on off and 1 programmable connector on detachable screw terminals 12 VDC 0 5 amps each RS 232 Serial Input Output 2 9 pin D sub connectors Power Requirements 120 230 VAC 50 60Hz 1300W universal line input detachable power cord Dimensions Weight Height with feet 7 76 inches ...

Page 16: ...ammed learning Requires 4 AAA batteries alkaline batteries recommended FM Tuner Performance Tuning Range 64MHz to 108MHz Usable Sensitivity 4uV 1 6uV typical Selectivity 87dbmV 93dbmV typical Frequency Response 50Hz to 16kHz 0 1dB 1 0dB THD Noise Below 0 4 at 1 kHz stereo Signal to Noise Ratio 50dB minimum at 60dBmV stereo A Wtg Image Rejection 50dB 60dB typical AM Suppression 45dB 55dB typical AM...

Page 17: ...B at 10Hz THD Noise Below 0 02 20Hz to 20kHz 4 7mV input Signal to Noise Ratio 72dB minimum Compatible Amplifier Connectors Banana Plugs Standard 0 75 inch plugs Spade Connectors Size 10 12 gauge Bare Wire Up to 10 gauge bare wire Specifications are subject to change without notice 3 5 ...

Page 18: ...RV 8 Service Manual 3 6 ...

Page 19: ...ower supply J14 220VAC J15 120VAC 7 Put the cover back on 8 Connect the AC cord Using the main power switch on the back of the RV 8 verify that the unit runs through its Power On Diagnostics 9 Check each of the front panel switches for smooth mechanical operation Verify each LED turns on and off when the associated switch is depressed and that the display acknowledges each switch function 10 Press...

Page 20: ...power switch of the RV 8 to the 0 OFF position 2 Disconnect the AC Line cord from the unit 3 Plug the transformer primary wiring harness into the connector J15 120VAC on the Power Supply Board to the left of the transformer 4 Set the Digital Multi Meter DMM for a DC resistance reading on the highest range 5 Set the rear panel power switch of the RV 8 to the 1 ON position Test 1 Verify the resistan...

Page 21: ...e current draw on the Variac after approximately sixty seconds verify that the current draw is less than 1 0A 0 85A typical and all seven amplifier channel LEDs are lit Brown Out Test This test verifies that the unit responds to a brown out reduction in AC Line Voltage Setup 1 The RV 8 should be powered on normally through the Variac 2 Wait for the RV 8 to complete its power up initialization 3 Ve...

Page 22: ...are removed the amplifier channels carry a lethal voltage Stay clear of them when testing the inside of the RV 8 When replacing the channels it is important to discharge them before removing them from the chassis Follow the safety and handling procedures below when service is required inside the RV 8 Discharging The Power Supply 1 The unit must be disconnected from the AC Power before it is discha...

Page 23: ...V 50 60Hz Item Description 120VAC 220 240VAC 1 AC Fuse on Power Supply PCB 440 16213 15A 440 16212 6 3A 2 Transformer primary wire harness Plug to 100V 120V connector J15 Plug to 220V 230V 240V connector J14 Measuring Power Supply Voltages In this procedure testing of the supplies will be performed with the top cover removed and the unit turned on Due to risk of shock do not remove the cover with ...

Page 24: ...to the external amplifier left and right inputs Connect the outputs of the external amplifier to the pair of speakers 3 Power on the RV 8 4 Press the remote control MAIN soft button 5 Press the remote TUNER soft button 6 The RV 8 s display will display Tuner in the upper left and the AM or FM radio station it is tuned to in the upper right 7 Raise the RV 8 volume to a comfortable level 8 Randomly ...

Page 25: ...ring the transmitted signal at pin 2 to the received signal at pin 3 Test 1 Connect the video monitor to the main composite video output of the RV 8 and turn the monitor on This will allow full viewing of the RV 8 s Diagnostics menus 2 Power on the RV 8 using the main power switch on the rear panel 3 When LEXICON appears on the display press and hold the Zone2 DVD2 and Zone3 DVD2 buttons on the fr...

Page 26: ...nu arrows and highlight SETUP Press the Menu arrow to enter SETUP 3 In the SETUP menu highlight INPUTS Press the Menu arrow to enter INPUT SETUP 4 Highlight DVD1 and press the Menu arrow button to select the DVD1 INPUT SETUP menu 5 Scroll down through the DVD1 menu options and highlight ANALOG IN Press the Menu arrow to enter DVD1 ANALOG IN 6 Scroll through the DVD1 ANALOG IN input options and hig...

Page 27: ...ress the remote control Menu arrow 2 Scroll through the MAIN MENU using the arrows and highlight SETUP Press the Menu arrow to enter SETUP 3 In the SETUP menu highlight INPUTS Press the Menu arrow to enter INPUT SETUP 4 Highlight DVD1 and press the Menu arrow to select the DVD1 INPUT SETUP menu 5 Scroll down through the DVD1 menu options and highlight ANALOG IN Press the Menu arrow to enter DVD1 A...

Page 28: ... 5 Scroll down through the DVD1 menu options and highlight ANALOG IN Press the Menu arrow to enter DVD1 ANALOG IN 6 Scroll through the DVD1 ANALOG IN input options and highlight ANALOG 1 Press the Menu arrow to assign the input to DVD1 7 Press the Menu arrow once to return to the DVD1 INPUT SETUP menu 8 Scroll down through the menu and highlight ZONE2 IN Press the Menu arrow to select the ZONE2 IN...

Page 29: ...MENU using the Menu arrows and highlight SETUP Press the Menu arrow to enter SETUP 3 In the SETUP menu highlight INPUTS Press the Menu arrow to enter INPUT SETUP 4 Highlight DVD1 and press the Menu arrow to select the DVD1 INPUT SETUP menu 5 Scroll down through the DVD1 menu options and highlight DIGITAL IN Press the Menu arrow to enter DVD1 DIGITAL IN 6 Scroll through the DVD1 DIGITAL IN input op...

Page 30: ...kers 3 Power on the external amplifier Slowly increase the volume on the external amplifier to a comfortable listening level 4 Sweep the oscillator from 20Hz to 20kHz Verify that clean undistorted audio can be heard throughout the frequency sweep 5 Power down the external amplifier 6 Switch from the Zone 2 Fixed outputs to the Zone 2 Variable outputs and repeat steps 3 to 5 above Phono Input to Zo...

Page 31: ...AT machine 3 Connect the left and right analog outputs of the DAT machine to the analog left and right inputs of the external amplifier Connect the outputs of the external amplifier to a pair of speakers 4 Place the DAT machine into Record mode 5 Power on the external amplifier Slowly increase the volume on the external amplifier to a comfortable listening level 6 Sweep the oscillator from 20Hz to...

Page 32: ... DVD1 DIGITAL IN selected in step 6 to the next appropriate input 11 Now test the optical inputs using steps 1 to 10 Be sure to use the appropriate digital cable AUDIO I O TESTS In order to properly test the RV 8 as described in this procedure the RV 8 must be in Diagnostics mode Perform the following procedure to enter the Diagnostics mode To enter Diagnostics mode 1 Connect the video monitor to ...

Page 33: ...uts labeled 1 to 8 and all analog amp output channels Test 1 Connect the low distortion oscillator output to the left and right analog audio inputs labeled 1 on the rear panel of the RV 8 2 With the RV 8 powered off connect the RV 8 amplifier front left and front right outputs to the pair of speakers 3 Power on the RV 8 4 Using the Menu arrows scroll through the Diagnostics Menu and select the AUD...

Page 34: ...est This test will verify the audio path between the S PDIF coaxial and optical digital audio inputs labeled 1 to 4 and all Main Zone analog outputs Note This test requires the use of a CD player as a source The tests to follow will be run using a PCM signal at a 44 1kHz sample rate Test 1 Connect the S PDIF coaxial digital output of the CD player to the S PDIF coaxial digital input 1 on the RV 8 ...

Page 35: ...the Menu arrows scroll through the Diagnostics Menu and select the AUDIO I O TESTS 4 In the AUDIO I O TEST menu highlight S PDIF INPUT CX 1 TEST Press the remote control Menu arrow to engage the test The RV 8 is now set to route digital audio from the S PDIF coaxial digital input labeled 1 to all the RCA analog outputs 5 Power on the external amplifier Press play on the CD player 6 Slowly increase...

Page 36: ...iagnostics Menu and select the AUDIO I O TESTS 4 In the AUDIO I O TEST menu highlight S PDIF INPUT CX 1 TEST Press the remote control Menu arrow to engage the test The RV 8 is now set to route digital audio from the S PDIF COAX digital input labeled 1 to all the RCA analog outputs 5 Power on the external amplifier Press Play on the CD player 6 Slowly increase the volume on the external amplifier t...

Page 37: ...log outputs Gain Test GAIN 1 Apply a 997Hz signal 4Vrms to the RV 8 left RCA analog input 1 2 Set the scale on the Distortion Analyzer to measure 8Vrms signal level 3 Turn all the filters off on the Analyzer Filter not required for this test 4 Verify that the output level measurement from the RV 8 is between the range of 3 10Vrms and 3 70Vrms Note this level Total Harmonic Distortion Test THD 1 Ad...

Page 38: ...he RV 8 is now set to route audio from the left and right RCA inputs labeled 1 to all amplifier outputs Gain Test GAIN 1 Apply a 1kHz signal 1Vrms to the RV 8 Left RCA analog input 1 2 Set the scale on the Distortion Analyzer to measure 8Vrms signal level 3 Turn all the filters off on the Analyzer Filter not required for Gain Test 4 Verify that the output level measurement from the RV 8 is between...

Page 39: ...he Menu arrow to engage the test The RV 8 is now set to route audio from the left and right RCA inputs labeled 1 to all RCA analog outputs Gain Test GAIN 1 Apply a 997Hz signal 0dBFS to the S PDIF coaxial 1 input of the RV 8 2 Set the scale on the Distortion Analyzer to measure 8Vrms signal level 3 Turn all the filters off on the Analyzer Filter not required for Gain Test 4 Verify that the output ...

Page 40: ... from the DVD player to the RV 8 s composite video input 1 2 Connect the first main composite output of the RV 8 to the composite input of the video monitor 3 Turn on the DVD player monitor and the RV 8 4 The monitor should display a blue screen 5 Press the remote control MAIN button then press the DVD1 button to select DVD1 as the input for testing the video paths 6 Press the Menu arrow to displa...

Page 41: ...teps 1 to 3 of this test procedure 8 Repeat step 7 above to test the remaining RV 8 composite inputs 3 through 5 S video Inputs to S video Outputs Test This test will verify the S video switching function of the RV 8 Setup 1 Connect the S video output from the DVD player to the RV 8 S video input 1 2 Connect the first main S video output of the RV 8 to the S video input of the video monitor 3 Turn...

Page 42: ...he DVD player 5 Repeat the above procedure for the two Zone 2 S video outputs 6 To test the remaining S video inputs 2 through 5 reconnect the S video output cable to the first main S video output 7 In steps 13 and 14 of the above Setup procedure change the VIDEO IN parameter from S VIDEO 1 to S VIDEO 2 Repeat steps 1 to 3 of this test procedure 8 Repeat Step 7 above to test the remaining RV 8 S v...

Page 43: ... Load a disc into the DVD player and press play 2 Verify a clean undistorted picture appears on the monitor 3 Pause the DVD player 4 In steps 13 and 14 of the above Setup procedure change the COMPONENT IN parameter from COMPONENT 1 to COMPONENT 2 Repeat steps 1 to 3 of this test procedure 5 Repeat step 4 above to test the remaining RV 8 component inputs Composite Video Input to Component Video Out...

Page 44: ... arrow 20 The ON SCREEN DISPLAY menu will open with the STATUS parameter highlighted Select the STATUS parameter by pressing the Menu arrow and change the value of the parameter to ALWAYS OFF 21 Press the Menu arrow to exit the menu structure 22 The video path is now set for testing Test 1 Load a disc into the DVD player and press Play 2 Verify a clean undistorted picture appears on the monitor S ...

Page 45: ... with the ON SCREEN DISPLAY parameter highlighted Select it by pressing the Menu arrow 21 The ON SCREEN DISPLAY menu will open with the STATUS parameter highlighted Select the STATUS parameter by pressing the Menu arrow and change the value of the parameter to ALWAYS OFF 22 Press the Menu arrow to exit the menu structure 23 The video path is now set for testing Test 1 Load a disc into the DVD play...

Page 46: ...2 Adjust R252 until the voltage measured is 350mV 12mV 338mV 362mV Channel 4 1 Measure the DC voltage across pins 5 6 of P11 2 Adjust R336 until the voltage measured is 350mV 12mV 338mV 362mV Bias Adjustment On The 3 Channel Module Note The reference designators on the 3 Channel Module are identical to the 4 Channel Module except Channel 1 is eliminated Channel 2 1 Measure the DC voltage across pi...

Page 47: ...ion test settings and parameters used by Lexicon in production testing of all RV 8 products The ATE chart and ATE summary are provided as a reference and supplement of bench test settings found in the rest of the Performance Verification chapter The Audio ATE Test Chart is located on the next page ...

Page 48: ...TO_DIG_ZONE2_COAX_OUT_96K_XTALK 1 4 00 Vrms 4 00 Vrms 15k None 20 Unbal Float dB Level 86 00 80 00 130 00 n a 10 Fs 2 None n a n a 7 19 Internal 96000 Analog ANLG_ZONE2_IN7_TO_DIG_ZONE2_COAX_OUT_96K_DYNRNG 1 4 00 mVrms 4 00 mVrms 997 None 20 Unbal Float dBFS THD N 107 00 104 00 130 00 n a 10Hz 20kHz LP Narrow n a n a 7 19 Internal 96000 Analog ANLG_ZONE2_IN8_TO_DIG_ZONE2_COAX_OUT_96K ANLG_ZONE2_IN...

Page 49: ...og ANLG_FRONT_IN1_TO_DIG_ZONE2_OPT_OUT_44K_THD 1 3 80 Vrms 3 80 Vrms 997 None 20 Unbal Float dBFS THD N 99 00 88 00 120 00 n a 10 Fs 2 None n a n a 1 13 Internal 44100 Analog ANLG_FRONT_IN1_TO_DIG_ZONE2_OPT_OUT_44K_DYNRNG 1 4 00 mVrms 4 00 mVrms 997 None 20 Unbal Float dBFS THD N 107 00 104 00 130 00 n a 10Hz 20kHz LP Narrow n a n a 1 13 Internal 44100 Analog ANLG_FRONT_PHONO75_IN_TO_DIG_ZONE2_OPT...

Page 50: ...External 44100 Digital DIG_ZONE2_COAX4_IN_44K_TO_ANLG_ZONE2_VAR_OUT_THD 1 12 00 dBFS 12 00 dBFS 997 None n a n a n a THD N 002 005 0002 100k 10 22k None 7 19 n a n a External 44100 Digital DIG_ZONE2_OPT1_IN_44K_TO_ANLG_ZONE2_VAR_OUT DIG_ZONE2_OPT1_IN_44K_TO_ANLG_ZONE2_VAR_OUT_GAIN 1 0 00 dBFS 0 00 dBFS 997 None n a n a n a Vrms Level 4 20 4 50 3 590 100k 10 500k None 7 19 n a n a External 44100 Di...

Page 51: ... 00 Vrms 4 00 Vrms 15k None 20 Unbal Float dB Level 95 00 75 00 150 00 100k 10 22k None 5 17 4 16 Internal n a Analog ANLG_ZONE3_IN4_TO_ANLG_ZONE3_DIR_VAR_OUT_SNR 1 OFF OFF 997 None 20 Unbal Float dBr Level 110 00 105 00 140 00 100k 10 22k None 5 17 4 16 Internal n a Analog ANLG_ZONE3_IN5_TO_ANLG_ZONE3_DIR_VAR_OUT ANLG_ZONE3_IN5_TO_ANLG_ZONE3_DIR_VAR_OUT_GAIN 1 4 00 Vrms 4 00 Vrms 997 None 20 Unba...

Page 52: ...NR 1 OFF OFF 997 None 20 Unbal Float dBr Level 112 00 102 00 140 00 600 10 22k None 11 23 1 13 Internal n a Analog ANLG_ZONE3_IN1_TO_ANLG_ZONE3_HEADPHONE_OUT ANLG_ZONE3_IN1_TO_ANLG_ZONE3_HEADPHONE_OUT_GAIN 1 4 00 Vrms 4 00 Vrms 997 None 20 Unbal Float Vrms Level 4 36 4 60 4 14 600 10 500k None 11 23 3 15 Internal n a Analog ANLG_ZONE3_IN1_TO_ANLG_ZONE3_HEADPHONE_OUT_FREQ 1 2 00 Vrms 2 00 Vrms 10 2...

Page 53: ...og ANLG_MAIN_DIR_IN345_TO_ANLG_MAIN_AMP4_OUT_XTALK 2 1 00 Vrms 1 00 Vrms 1k 20k None 25 Unbal Float dB Level 58 00 55 00 150 00 100k 10 22k None 1 2 3 0 3 0 Internal n a Analog ANLG_MAIN_DIR_IN345_TO_ANLG_MAIN_AMP5_OUT_XTALK 2 1 00 Vrms 1 00 Vrms 1k 20k None 25 Unbal Float dB Level 58 00 55 00 150 00 100k 10 22k None 6 7 0 1 0 Internal n a Analog ANLG_MAIN_DIR_IN345_TO_ANLG_MAIN_AMP6_OUT_XTALK 2 1...

Page 54: ......

Page 55: ... front panel standby button or the remote control SYSTEM OFF button will put the unit into a low power standby mode When the RV 8 is in standby mode pressing any of the front panel or remote control Main Zone 2 or Zone 3 input select buttons and or pressing the front panel standby button or the remote control POWER button will bring the RV 8 out of standby mode No diagnostics are run when the unit...

Page 56: ...tc can be viewed on the VFD display or it can be sent to the serial debug port Vacuum Fluorescent Display VFD The VFD is the primary source of information during diagnostics The exact display information will depend on the test s being executed When an individual diagnostic test is executed the VFD will display the name of that test Groups of tests such as the power on diagnostics have a generic m...

Page 57: ... a D9 for both COM 1 and COM 2 The COM port used on the computer does not matter however you must ensure that whatever serial communications program is being used has the correct computer COM port selected Serial Debug Program The serial debug program controls the communication from an RV 8 to a computer This program allows a user to view activity of the unit and to control and configure the unit ...

Page 58: ...RROR_PARAM_SEMA_CREATE 0x60 CS49400_NO_BOOT_START_MESSAGE 0x100 CS49400_NO_BOOT_SUCCESS_MESSAGE 0x101 CS49400_INIT_ERROR 0x102 CS49400_ERR_WRITE_TIMEOUT 0x103 CS49400_ERR_READ_TIMEOUT 0x104 CS49400_INTREQ_TIMEOUT 0x105 CS49400_AUTO_BOOT_FAILURE 0x106 CS49400_ENQ_MSG_FAILURE 0x107 CS49400_DEQ_MSG_FAILURE 0x108 CS49400_FINTREQ_TIMEOUT 0x109 CS49400_NO_APP_START_MESSAGE 0x110 CS49400_AB_SPI_TIMEOUT 0...

Page 59: ...dicates time out B1 WRITE Time out 1 is means there was a time out B0 SHARC processor id 0 is for Processor A and 1 for Processor B Bits B2 B1 and B0 are read together If a time out occurs then B2 or B1 will indicate what operation caused the fault B0 will indicate which processor failed Processor A or B Bit B3 is used to indicate whether the SHARC was able to run the code If this bit is zero the ...

Page 60: ...lanations The front panel display is shown only for the first test that can use the VFD The reference designators used are from Revision 5 Main Board 710 15550 used on BOM 023 15615 The schematics for the main board are 060 15559 Trap Opcode The Trap Opcode error occurs if during the initial boot sequence an undefined Opcode is fetched The INT TRAP Control register can be used to determine the sta...

Page 61: ...D matrix The test number will be read out as in the top row The error number can be read out in the second row Most Significant Byte and third row Least Significant Byte AVRX FPGA Test The AVRX FPGA test verifies the ID register can be read from the XC2S200 on the main board If a failure occurs the test will attempt to write the test number and the error number to the VFD CS49400 Test This test ve...

Page 62: ...s and the Functional suite comprise the automated sets of tests used to verify proper operation of every unit Each of the tests in these suites are run in order unless there is a failure The failing test will loop to allow the electrical signals to be active for troubleshooting You can optionally continue to run the other diagnostic tests in the suite The Repair suite allows you to run particular ...

Page 63: ... of tests that deal with a portion of the board For example the SHARC tests and the Trigger tests can be placed in sub menus In the repair suite the SHARC tests will also include tests as outlined below SHARC WCLK SHARC BOOT PAIR 0 PAIR 1 SHARC SDRAM PAIR 0 PAIR 1 SHARC WCLK PAIR 0 PAIR 1 In the repair suite the ability to set each trigger on and off will be available SET TRIGGERS Trigger 0 ON Tri...

Page 64: ... 3 RELAY OFF ON CHANNEL 4 RELAY OFF ON CHANNEL 5 RELAY OFF ON CHANNEL 6 RELAY OFF ON CHANNEL 7 RELAY OFF ON ALL RELAYS RELAY OFF ON SET FAN TEST FAN SPEED 0 3 THERMOSTAT TEST AMP 1 7 HEADPHN INSERTION EXPANSION BRD TEST DIG RCVR LOCK TEST SHUT OFF HV AMP PWR SET CONSTANT CYCLE NORMAL OPERATION The repair diagnostic tests that are the same as in the power on diagnostic tests and functional diagnost...

Page 65: ... the VFD display light RED AMBER and BLUE 2 In approximately three seconds verify the display indicates LEXICON 3 When the LEXICON display appears within eight seconds press and hold the Zone 2 DVD2 and Zone 3 DVD2 buttons 4 The display indicates a display similar to the following Note that the BOOTROM revision date XX XX and time XX XX will contain valid digits LEXICON RV 8 BOOTROM 200X XX XX XX ...

Page 66: ...d the front panel display should indicate RS232 WRAP TEST Insert Wrap Plugs RS232 Wrap Test This test verifies that the unit can communicate with the rear panel serial communication connectors Setup 1 Create two 2 RS 232 wrap around plugs by connecting pins 2 3 of a female DB9 connector 2 Install the two RS 232 wrap around plugs onto the RS 232 1 and 2 ports located on the RV 8 rear panel Test 1 P...

Page 67: ...The LCD display on the remote control should appear as in Figure A below 2 Press the top left MAIN button once to open the MAIN menu The LCD display on the remote control should appear as in Figure B below Figure A HOME MENU Figure B MAIN MENU Note The RV 8 will NOT respond to the PAGE HOME FAV M1 M2 and M3 buttons 3 RV 8 Setup The front panel display should indicate IR REMOTE TEST Remote Test 5 1...

Page 68: ...e display indicates 5 Press the Mode button to proceed to the next test Display Block Test This test verifies that the unit can display all the pixels in one block at a time Test 1 Verify the display has one block lit with no missing pixels in the top left corner of the display 2 Turn the encoder knob clockwise until all forty blocks have been displayed Note The blocks along the top row will be li...

Page 69: ...h Name is the name of the Switch that is labeled on the front panel When all twenty two switches have been pressed the display will indicate SWITCH TEST All Switches Done 2 Press the Mode button to proceed to the next test Encoder Test This test verifies the operation of the encoder knob Setup The front panel display should indicate ENCODER TEST ENCODER Test Test 1 Turn the encoder knob clockwise ...

Page 70: ...t LED Color CODE LED COLOR 11 Standby RED 12 Ready BLUE 49 IR Ack YELLOW 50 Overld RED 51 Sys ON BLUE 10 Mute YELLOW MAIN 0 Main DVD1 BLUE 2 Main Sat BLUE 4 Main TV BLUE 6 Main Tuner BLUE 1 Main DVD2 BLUE 3 Main VCR BLUE 5 Main CD BLUE 7 Main Phono BLUE 9 Main OFF RED ZONE2 16 Zone2 DVD1 YELLOW 18 Zone2 SAT YELLOW 20 Zone2 TV YELLOW 22 Zone2 Tuner YELLOW 17 Zone2 DVD2 YELLOW 19 Zone2 VCR YELLOW 21...

Page 71: ...dphone Insert Test This test verifies that the RV 8 can detect the presence of headphones plugged in to the front panel Phones jack Setup The front panel display should indicate HEADPHN INSERT TEST HDPhones OUT Test 1 Insert a 1 4 inch headphone plug into the Phones jack on the RV 8 front panel and verify that the display indicates HEADPHN INSERT TEST HDPhones IN 2 Remove the 1 4 inch headphone pl...

Page 72: ... RV 8 chassis Two fans are on the left side and two are on the right side of the unit Setup The front panel display should indicate FAN TEST FAN Speed 0 Test 1 Turn the encoder knob slowly clockwise until the display indicates FAN Speed 1 2 Verify that the fans have started turning 3 Turn the encoder knob slowly clockwise until the display indicates FAN Speed 2 4 Verify that the speed of the fan s...

Page 73: ... 8 chassis 5 Store the module in a static free area To remove the amp channels 1 For ease of removal of the left 3 channel amp remove the switching power module first 2 Locate and disconnect the black 6 wire connector and two thin white ribbon cables that run to the main analog board at J18 and J21 Also remove one large thin white ribbon cable on the underside of the amp channel connecting to J22 ...

Page 74: ...nect the following cables J2 5 6 7 21 and P1 2 Turn the RV 8 over and remove the ribbon cable J20 that runs to the front panel 3 Remove the six screws that hold the assembly in place three on each amp channel side 4 Carefully grab on to the assembly and pull up removing it out the bottom of the RV 8 chassis 5 Store it in a static free area To remove the Tuner Phono Board 1 Place the RV 8 upside do...

Page 75: ... panel 1 Place the RV 8 upside down with the front panel facing you 2 Locate and remove the two screws and ribbon cable J20 and disconnect it from the Main board 3 Turn the RV 8 over Locate and remove the two screws holding the front panel to the chassis 4 Carefully pull the front panel away from the chassis and store it in a static free area 5 21 ...

Page 76: ......

Page 77: ...onversion stage The overall gain of this stage is approximately 6 15 6dB which is set by R2 2 49k R4 2 49k R3 15k and R5 15k C1 22pF provides high frequency feedback Power Amplifier Overall Gain For this portion of the theory consider the power amplifier as one large op amp The output of U1 A MC33078 feeds a single ended audio signal into the power amplifier The power amplifier is set up as a conv...

Page 78: ...nt of the amplifier is sensed across emitter resistors R26 0 68 R27 0 68 R169 0 68 and R173 0 68 This information is summed via R342 23 2k and R343 23 2k then divided down by R344 1 82k and R345 100k The divided voltage information is fed into the base of Q77 KST5089 Once the voltage across R344 and R345 reaches approximately 0 65Vdc Q77 turns on which causes Q79 MMBT3906 to turn on as well This r...

Page 79: ...also protected from DC signals and Low Frequency LF signals The output is monitored and will open the relay if either of these conditions exists The relay will stay off for a few seconds and will try to turn back on If a DC or LF signal still appears at the output the relay will either turn off again or not turn on at all This cycle will repeat until a DC or LF signal is no longer present at the o...

Page 80: ...es eight different output signals from the 2 channel input D A converter IC s convert each of the eight signals from the DSP to analog and then send them to their respective RCA connectors The outputs are also sent to the seven channels of amplification with channels 6 and 7 having the ability to be redirected A direct analog path is provided which passes a 2 channel analog input signal directly t...

Page 81: ... sw Main Mux sw 6 7 Mux Front L R Mux Ctr Sub Mux Side L R Mux sw sw sw sw sw sw main clks sw sw Rear Mux C Sub Side 1 2 3 4 5 6 7 Main Main to Amps 4 7 8 5 Rear Level Rear Direct Rear Direct C Sub Side Zone2 and Zone3 Audio Paths Any of the ten analog or eight digital audio inputs can also be selected as the source for the Zone2 and Zone3 audio paths Refer to the Zone2 and Zone3 Audio Paths block...

Page 82: ...to the Main Input level control and A D converter These switches work in parallel with the muxes on sheets 1 and 2 to provide a 1 of 12 analog input function When the Mic input is selected the Analog inputs are disabled by bringing MAIN_ANLG_EN low on sheets 1 and 2 The Main Input level control is the PGA2311 which has a range from 31 5 to 95 5 dB in 0 5 dB steps The PGA2311 operates on 5 volt rai...

Page 83: ...ath The D A circuitry is shown for two outputs on each sheet The circuitry is identical for all eight outputs The AK4395 is the same 24 bit D A converter that operates Zone2 The AK4395 DACs are configured through their serial ports pins 8 10 11 MAIN_DAC_RST puts the pairs of DACs into reset The DACs are followed by a 2nd order low pass filter The filter topology is a flat pass band Butterworth fil...

Page 84: ... a separate buffer and source resistor The SCLK 64xFS and LRCK 1xFS are distributed directly to the DACs All of the D A converters operate in I2S mode J20 and J22 provide a row of test points for quick access to all the clocks J23 and J24 are ribbon connectors from the Mic Phono Board and Tuner board respectively The left and right signal pairs are buffered differentially and presented to the inpu...

Page 85: ...e unit is powered up the reset generator U31 provides both active low and active high reset signals of approximately 3ms duration During this interval the CPU processor U33 is held in an inactive state as well as the three DSP engines and the FPGA This reset is also passed along to all of the remaining boards in the system Once this reset interval has passed the processor and FPGA are ready for fu...

Page 86: ...or Sheet 1 This page contains the embedded CPU and its associated DRAM and flash memory for storage of the boot mode and system control software In addition provisions are in place for a separate boot flash memory and emulator support during software development Processor U33 The processor is a Hitachi SH7014 single chip RISC This device implements all system control via a 16 bit wide data bus ove...

Page 87: ...and a second one when it is released This is CPU_KYBDIRQ IRQ1 46 is currently unused It may be used as an interrupt source monitor or a general purpose I O in the future IRQ2 43 monitors the status of the SPI port transfers to and from the algorithm DSPs Currently this interrupt is masked off by the system software but it remains as a provision This is CPU_DSPABIRQ IRQ3 42 monitors the status of I...

Page 88: ...ns are to run Under extreme heating conditions the CPU protects the amplifiers from thermal runaway by placing the entire system into standby mode The processor incorporates four Multi Function Timer Units that may be used to generate timing oriented waveforms or as interval event counters Two are used in this implementation Timer 1 generates a PWM signal that is used to control environment fans T...

Page 89: ...he event timer is restarted and the period is verified by count value FLBY is output from the storage FLASHRAM U26 to indicate that the device is busy either during an erase or re programming operation The processor device monitors this signal via the PE14 port 1 When the signal is low the FLASHRAM is not ready for read accesses When high the device may be accessed as normal DRAM U42 The DRAM used...

Page 90: ... or in circuit programming is accomplished by executing the erase or program command sequence These sequences initiate the proper embedded algorithm that ensures proper execution of the desired command The RESET pin 12 is tied to the system level power on reset When this pin is low it suspends any operation that is in progress and resets the internal state machines to reading array data During pow...

Page 91: ...est point E6 has been provided so that manual triggering of the reset may be accomplished by connecting the test point to ground momentarily This saves the trouble of having to power cycle the entire unit C111 provides high frequency filtering of the internal voltage reference at the REF pin 1 R113 provides a default pull up for the RESET pin 5 while R112 provides a default pull down of the RESET ...

Page 92: ... a reliable switching characteristic while C159 and C160 provide the proper AC load to the reactive element of Y2 The second stage of this circuit is another gate from the hex package that simply buffers the output of the oscillator presenting a minimal load to it while providing drive capability Final buffering to the remainder of the 5V domain of this board is provided by yet another gate from U...

Page 93: ...ts Device Pins IRQ2 J1 IRQ1 H4 IRQ0 H2 The ADSP21161N has provision for three interrupt sources In this application only one is used IRQ0 with the unused IRQ lines pulled to an inactive high state IRQ0 monitors an active low interrupt provided by the FPGA which is generated coincident with the rising edge of the word clock divided by eight i e 14 112MHz 8 1 764MHz Therefore for every eight audio s...

Page 94: ...fault to input mode Note that FLAG0 is no longer used in this application Its function is non descriptor Proprietary DSP A SDRAM and Flash Sheet 4 This sheet shows the interconnection between DSP A and its SDRAM It also illustrates the boot configuration for DSP A SDRAM U6 Each SHARC is supported by a 2 Mbit x 32 100MHz SDRAM The memory interface is implemented as four banks of 256 words Each succ...

Page 95: ... 7 0 Memory access is contiguous with this scheme The following diagram illustrates how each 256 word page is interleaved in relation to the internal address Memory Interleave Diagram Bank 0 0x000000 0x0000FF Bank 1 0x000100 0x0001FF Bank 2 0x000200 0x0002FF Bank 3 0x000300 0x0003FF 1024 Words Bank 0 0x000400 0x0004FF Bank 1 0x000500 0x0005FF Bank 2 0x000600 0x0006FF Bank 3 0x000700 0x0007FF 1024 ...

Page 96: ...een DSP B and its SDRAM It also illustrates the boot configuration for DSP B The functionality of this page is identical to that of Sheet 4 Further discussion would be redundant DSP SPI Serial and Link Ports Sheet 6 This sheet shows the interconnection between DSP A and DSP B as well as the SPI host interface as well as the audio data path into and out of the SHARCs SPI Interface Signals DSPASEL D...

Page 97: ...start signal The audio data entering U16 on DSPASP0FPGA is comprised of samples from either the system S PDIF inputs the outputs of the A D Converters from the Analog IO Board or the IP 2 PS streams output from the Format Decoder DSP The selection of which stream is sent along to the SHARC is done via data multiplexing within the AVRX FPGA The data is clocked into the input buffers on the SHARC by...

Page 98: ...ollowing equation VB OUT B VB REF B 1 R77 R78 IB ADJ B R78 Where VB REF B 1 25V IB ADJ B 60uA Substitute R143 for R77 R144 for R78 for U42 programming C67 and C127 provide local filtering of the 5V supply feeding the regulators C75 and C133 provide local bulk capacitance to the 1 8V planes for each SHARC At least one device from each of these pairs must be a low ESR tantalum type or the regulators...

Page 99: ...nsion Slot 0 Reset 0 Expansion Slot 0 is reset 1 Expansion Slot 0 is out of reset ETRGEN1 External Trigger 1 Enable 0 External Trigger 1 is inactive 1 External Trigger 1 is active ETRGEN0 External Trigger 0 Enable 0 External Trigger 0 is inactive 1 External Trigger 0 is active DSPCRST Format DSP Reset 0 CS494001 is in reset 1 CS494001 is out of reset DSPBRST SHARC U33 Reset 0 U33 is in reset 1 U33...

Page 100: ...D12 D13 D14 D15 BOOTLOCK SOFTRLY CPULED6 Test LED D10 0 D10 is off 1 D10 is lit CPULED5 Test LED D11 0 D11 is off 1 D11 is lit CPULED4 Test LED D12 0 D12 is off 1 D12 is lit CPULED3 Test LED D13 0 D13 is off 1 D13 is lit CPULED2 Test LED D14 0 D14 is off 1 D14 is lit CPULED1 Test LED D15 0 D15 is off 1 D15 is lit BOOTLOCK Program Flash Boot Sector Lock 0 Boot sector is write protected 1 Boot secto...

Page 101: ...tions are not addressed for access the tristate buffer is disabled and the IO pins float Format DSP Sheet 8 This sheet contains the format DSP associated FLASH RAM algorithm memory timing circuitry and delay components necessary for proper interfacing between the DSP and RAM Format DSP U25 This device decodes all the canned algorithm information from the input data streams provided by the FPGA Thi...

Page 102: ...undTM DTS Virtual 5 1TM Surround 6 1 C O S 6 1 TM THX Surround EXTM THX Ultra2 CinemaTM The IP 2 PS audio streams coming in to the Format Processor are interrogated via the DSPAB SPI port and its status is reported back to the CPU The SPI port for DSPAB is selected by asserting CRY_FCS low CRY_FINTREQ is an open drain output that is asserted low when DSPAB has control data that requires the host C...

Page 103: ...ecoder at the PLLVDD pin C100 provides local bulk capacitance for this supply rail through the FILT1 pin The internal PLL circuitry requires external band pass filtering which is provided via the FILT2 pin by R99 C98 and C99 CLKSEL selects the source clock for all internal logic in the Format Decoder and is controlled by software When this signal is low the internal clock source is the internal PL...

Page 104: ...3 0 These are multiplexed to an eight channel serial interface that is in the Analog Devices SPORT mode This eight channel interface drives the SPORT inputs of the SHARCs The serial bits are synchronous with DEC_OUT_SCKI which is equal to 64 FS DEC_OUT_FSI is the audio output sample rate clock Output Port Map Table Pin Number Pin Name Signal Map 110 AUDATA0 DEC_SDO0 Left Right 109 AUDATA1 DEC_SDO1...

Page 105: ...Peripheral Interface SPI ports that provide the means for the host processor to communicate to the system peripherals It also has an I2C interface for host communication to the video codec and it has interfaces for the IR remote control and rotary encoder AVRX U41 Functionality is implemented within a Xilinx XC2S200 device This device contains 200 000 logic gates 75 264 bits of distributed RAM and...

Page 106: ...PU The direction of these level shifting transceivers is controlled by BUFDIR This signal is low during write cycles to the FPGA and high during read cycles from the FPGA CPU accesses to and from the FPGA are synchronous with the core frequency of the host processor 25MHz This clock is provided by the host to the FPGA as CPUCLKOUT RESET is a power up reset signal that clears the state of the inter...

Page 107: ...e front panel LED display and pushbutton matrix This signal is a return stream of data reporting front panel button status to the host CPU Changes in button status are serially transmitted to the AVRX FPGA where current status is XOR ed with the previous status of the last scan A retriggerable timer is armed whenever the XOR gate is activated indicating a change in any of the buttons This timer se...

Page 108: ...e input clock rate When low the Format Decoder runs at the higher frequency of its internal PLL The power up mode of this pin is low CRY_TXD transmits control data to the Format Decoder utilizing a modified SPI Serial to Parallel Interface protocol Control data is written to the internal Format Decoder SPI Control RAM by the system software and serially shifted out via this pin CRY_RXD receives co...

Page 109: ...e Format Decoder Audio data from the system S PDIF inputs or from the signal MAIN_I2S_IN1 is multiplexed down to this one signal DEC_MCKI is the bit clock of the DEC_SDI stream and equivalent to 256FS DEC_OUT_SCKI is the sample clock 64FS output from the Format Decoder Signals DEC_SDO 3 1 are synchronous with this clock DEC_OUT_FSI is the word clock output from the Format Decoder that marks the sa...

Page 110: ... that indicates the presence or absence of video synchronization from the Video Board This signal is stored in the Interrupt Status Register at bit 7 There is no interrupt assigned to this signal so the host processor simply polls this bit for its status OSD_CS is the chip select for the Fujitsu MB90092 OSD Controller device located on the Video Board This signal becomes active when transfers are ...

Page 111: ... Board Audio Interface Signals REC_ADC_FS REC_ADC_FS64 REC_DAC_FS REC_DAC_FS64 MAIN_FS MAIN_FS64 MAIN_I2S_OUT 4 1 REC_DAC_I2S_OUT MAIN_I2S_IN 4 1 MAIN_I2S_IN1 is the serial data stream sourced from the MAIN A D Converter on the Analog Board to the AVRX FPGA This IP 2 PS stream is the 24 bit left and right channel data encoded from a selected left right analog input pair the phono preamplifier micr...

Page 112: ...AC_I2S_OUT It is sourced from the AVRX to the Record Zone D A converter REC_DAC_FS64 is the serial clock for REC_DAC_I2S_OUT The Zone 2 left right VAR and FIX outputs are sourced by the Record Zone D A converter Power Amplifier SPI Control Signals CTRL_DATA STAT_DATA SER_CLKA DATA_LATCHA CTRL_DATB STAT_DATB SER_CLKB DATA_LATCHB STAT_DATA is the receive path from the four channel power amplifier Da...

Page 113: ...RDY_MON 7 5 Base 1 3 Not used Base 1 6 4 Clip indicator for channels 7 5 CLIP7 5 Base 1 7 Not used Three Channel Status RAM Table CTRL_DATB is the transmit path to the three channel power amplifier Control data from the Host CPU is loaded into an internal 2x8 bit RAM that is in turn serially shifted out to the three channel amplifier board The only control data currently being transmitted is in th...

Page 114: ...ssion as to the theory of VCO operation will be made later in this document MAIN_PLL_PUMP_UP is an active low signal that forces the master clock to increase in frequency when the master clock rate is lower than the reference frequency MAIN_PLL_PUMP_DN is an active low signal that forces the master clock from the VCO to decrease in frequency when the master clock rate is higher than the reference ...

Page 115: ...DIN on the schematic When configuration has completed the FPGA re asserts FPGA_DONE high This signal is inverted by a single gate inside U38 causing D46 to illuminate upon completion of the configuration operation This provides a visual cue as to when the FPGA is done XFLASH_CF is an output pin from the EPROM that allows the programming port connected to the EPROM to configure the FPGA Programming...

Page 116: ...o two resistors the opposite ends of which connect to J25 and J30 The effect is that the bus is shared between both connectors but each slot has it s own impedance path back to the FPGA pins Board Interconn Debug Sheet 12 This page contains all of the off board interconnections to the Front Panel Board Video Board Analog IO Board and Amplifier Modules This page also contains the Debug and User Acc...

Page 117: ...e RFI integrity of the amplifiers The SPI port signals SER_CLKA CTRL_DATA STAT_DATA and DATA_LATCHA are discussed in greater depth on page 6 38 and will not be expanded upon here Each channel amplifier contains a thermistor that monitors heat sink temperatures local to each channel s output transistors This information is provided to the A D inputs of the Host CPU in the form of a voltage that inc...

Page 118: ...ther information regarding these signals FP_SDATA_IN is the signal by which the AVRX FPGA receives data back from the CPLD on the Front Panel Board with regards to the status of the pushbutton array FP_SDATA_OUT is the signal by which the AVRX FPGA transmits data to the CPLD on the Front Panel Board in order to write to the LED array SDATA_CLK is the clock signal that controls the serial shift of ...

Page 119: ...not needed here CVID_ZON3 is a composite video analog signal that is sourced from a video selector that selects between one of five composite inputs or one of five S VIDEO inputs on the rear panel Amp Power Supply Connector J27 J27 is a 6 position FFC connector that provides enable controls for the Amplifier Power Supply Board Relays that activate the power amplifiers This connector also provides ...

Page 120: ...re presented to the AVRX FPGA right from these inputs Record Zone S PDIF Outputs A digital audio output for the Record Zone is sourced from the AVRX FPGA to a 74VHCT244 Octal Buffer U2 Two out of the available eight buffers are actually used The first output drives a TORX style optical output connector The second buffer output drives a voltage divider that reduces the CMOS level of the signal to o...

Page 121: ...own pulses from the FPGA are buffered by U19 and connected to schottky diodes D18 and D19 When no pulses are asserted the diodes are reverse biased and no current is injected into the summing node of U11 When the VCO frequency is too low D16 will be forward biased by the UPA pulses asserted low by U19 The resulting current through R46 will be integrated by feedback capacitors C41 and C42 This will...

Page 122: ...the 3 3V It has been determined that this precaution is not needed in this design and so these components are not used W6 provides a zero ohm path from the 5VD supply to the input of U38 Diode D48 ensures that the output voltage never assumes a level higher than 5VD which could cause destruction to U38 Fan Control Circuitry U47 inverts the pulses supplied by one of the PWM timer circuits inside th...

Page 123: ...e distribution of capacitive de coupling for each of the supply voltage zones Of the six voltage planes used in this project the 3 3VD supply is larger because a far larger percentage of the design uses 3 3V logic This plane therefore has more in the way of high frequency de coupling as well as evenly distributed bulk capacitance The 5VD plane area is the next largest It primarily supplies the Hos...

Page 124: ...ved An RC filter is created by 330 ohms and 10uF The 2 2K resistors provide current limiting and define the input impedance that the microphone sees at the input of the amplifier RV 8 TUNER BOARD THEORY This section provides a detailed description of the design theory embodied in the RV 8 Tuner Board Each section of this document will discuss the theory of each functional subset of this board and ...

Page 125: ...S signal to both the RDS and FM inputs of U2 Signal Processor U2 The signals provided by tuner module U4 are processed by U2 a Philips TEF6892H device This is a signal processor with on board DSP that is intended for use in car audio systems Although signal paths for Cellphone CD player and Cassette Tape are provided they are unused in this application All radio signal de multiplexing and enhancem...

Page 126: ... bulk de couples the 12Vdc driving both regulator circuits RV 8 VIDEO SYSTEM THEORY The RV 8 video section consists of three major functional blocks video switcher video converter and on screen display generator OSD The video assembly consists of three boards the Video In Board schematic 060 15509 the Video Out Board schematic 060 15519 and the Video Board schematic 060 15589 The RCA input and out...

Page 127: ...heet 7 Chroma selected by U22 MC is ac coupled by C127 and amplified by U28 also with gain slightly greater than two With a composite source selected U22 is forced to input 0 grounding the chroma channel The signal OSD_C_IN is distributed to output amplifiers U15 U27 U38 and U5 and also feeds the on screen display sheet 7 The dc level on the chroma channel of the selected source is fed to two dc a...

Page 128: ... is in use Multiplexer U13 feeds the input dc voltage to the dc amplifier formed by Q2 Q3 and Q1 to transfer dc voltage on the chroma input to the chroma output for S video switching purposes The Zone2 composite output from U18 feeds two 75 ohm outputs connecting to rca jacks on the Video Out board via ribbon cable J16 Zone3 Composite video Video board schematic sheet 4 Zone3 is an additional vide...

Page 129: ...omponent input rca jacks component inputs 1 2 3 feed a 3 wide two tier tree of double throw relays Each tier is comprised of a pair of dpdt relays The tree selects one of the input sets and presents it to the bank of final output relays The final tier of relays RY3 RY1 connects the output RCA jacks either to the selected component input or to the video converter One transistor driver is associated...

Page 130: ...at 1 MHz During routine OSD updating OSD_CS is level shifted by U35 becoming OSD_CS5 the OSD chip select The CPLD generates OSD_SCLKG from the VIDEO_SCLK and U35 drives OSD_SCLK5 to clock the data into the OSD chip Each logical transfer to the OSD chip consists of a pair of single byte transfers Sync Stripper DC Restorer Video board schematic sheet 7 Video from input amplifier U28 is fed through R...

Page 131: ...vity is the fetching of font patterns from U25 over the A 15 0 D 7 0 buses under the control of OSD U26 When necessary the host processor on the main board manages the programming of the font flash memory A large white box on the OSD is a symptom of an un programmed memory A control register transfer with bit 47 set initiates a font flash write cycle based on a state machine in the CPLD The CPLD a...

Page 132: ......

Page 133: ...2 14584 RESSM RO 5 1 10W 10K OHM 0603 17 00 R73 75 79 81 84 108 R114 116 132 140 R141 171 179 187 202 14585 RESSM RO 0 OHM 0603 20 00 R53 55 70 72 100 102 R105 107 128 130 R137 139 148 150 R158 160 166 202 14792 RESSM RO 5 1 10W 56 OHM 5 00 R161 164 167 202 15681 RESSM RO 5 1 10W 47 OHM 0603 1 00 R152 203 10424 RESSM RO 1 1 10W 4 99K OHM 4 00 R38 39 87 88 203 10896 RESSM RO 1 1 10W 1 00K OHM 4 00 ...

Page 134: ...45 12524 CAPSM CER 68pF 50V COG 5 1 00 C21 245 14588 CAPSM CER 01uF 25V X7R 10 06 21 00 C32 36 56 61 62 65 C70 71 77 79 102 103 C107 108 125 128 135 C138 148 154 164 245 14764 CAPSM CER 82pF 50V COG 5 1 00 C99 270 00779 FERRITE BEAD 4 00 FB1 2 16 18 270 11545 FERRITESM CHIP 600 OHM 0805 12 00 FB3 13 15 270 12323 FERRITESM CHIP 750 OHM 0805 1 00 FB14 270 15670 INDUCTORSM 220uH 20 1 2A 1 00 L2 300 1...

Page 135: ...ONN HDR 200 4MC PCRA 1 00 TRIGGERS J3 510 13147 CONN RCA PCRA 1FCG YEL GND 1 00 J7 510 13148 CONN RCA PCRA 1FCGX2V BLK GND 2 00 J1 2 510 13538 CONN RCA PCRA 1FCG BLK GND 1 00 J8 510 13840 CONN OPTO PCRA TORX173 6Mbps 4 00 CP1 4 510 14079 CONN POST 156X045 HDR 4MC LOK 1 00 J31 510 14833 CONN OPTO PCRA XMTR 13 2Mbps 1 00 12 13 04 CP5 510 15688 CONN FFC 1 25MM 16 POS VERT 1 00 VIDEO BD J29 510 15689 ...

Page 136: ...F 50V COG 10 6 00 C1 4 25 27 245 10974 CAPSM CER 4 7pF 50V COG 5 2 00 C41 44 245 10976 CAPSM CER 47pF 50V COG 5 6 00 C11 12 15 16 19 22 245 12485 CAPSM CER 1uF 25V Z5U 20 10 00 C13 14 17 20 21 C23 34 35 42 43 245 12522 CAPSM CER 120pF 50V COG 10 2 00 C29 30 270 11545 FERRITESM CHIP 600 OHM 0805 8 00 FB1 8 300 10563 DIODESM DUAL SERIES GP SOT23 8 00 D1 6 13 14 300 10564 DIODESM SCHOTTKY LOW VF SOT2...

Page 137: ...1 430 14487 LED T1 BLU 430NM 1 00 SYSTEM ON D4 430 14787 LED T1 RED 700NM 1 00 OVERLOAD D2 430 14788 LED T1 YEL 585NM 1 00 IR ACK D3 452 13640 SW RTY ENC 24POS INC B 25L VRT 1 00 SW1 630 14778 SPCR LED T1 375 H 3 00 D2 4 680 14082 CABLE 100 PLUG SCKT 2X7C 3 L 1 00 IR ENC BD J1 TO SW LED BD 710 13690 PC BD IR ENC MC12 1 00 PICK REV 2 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 Switch LED Board As...

Page 138: ...7 R271 275 202 10570 RESSM RO 5 1 10W 120 OHM 11 00 R18 22 28 32 98 101 R111 301 404 415 417 202 10571 RESSM RO 5 1 10W 100K OHM 40 00 R50 51 54 55 58 59 R62 63 66 67 70 71 R74 75 78 79 113 117 R120 126 129 132 135 R238 240 244 246 250 R252 256 258 261 264 R268 272 276 390 406 R413 414 202 10585 RESSM RO 5 1 4W 51 OHM 18 00 R106 108 278 281 282 R285 286 289 290 293 R314 317 322 325 330 R333 338 34...

Page 139: ... 38 39 42 43 R46 47 92 97 99 100 203 12969 RESSM THIN 1 1 10W 316 OHM 20 00 R212 215 220 235 203 13133 RESSM THIN 1 1 10W 1 15K OHM 8 00 R164 169 174 179 R184 189 194 199 203 13537 RESSM THIN 1 1 10W 5 62K OHM 8 00 R262 265 266 269 R270 273 274 277 203 13638 RESSM THIN 1 1 10W 2 49K OHM 8 00 R279 280 283 284 287 R288 291 292 203 15237 RESSM THIN 1 1 10W 681 OHM 4 00 R208 211 216 219 203 15479 RESS...

Page 140: ...252 254 258 260 245 11949 CAPSM CER 1500pF 50V COG 5 4 00 C230 231 234 235 245 12316 CAPSM CER 0082uF 50V X7R 10 7 00 C227 228 368 370 C470 471 475 245 12485 CAPSM CER 1uF 25V Z5U 20 238 00 C33 34 37 38 41 42 C45 46 49 50 53 54 C57 58 61 62 77 85 C87 88 90 92 94 95 C97 111 114 116 119 C122 124 127 140 143 C144 147 152 154 155 C158 159 162 163 166 C167 169 193 196 197 C202 203 208 209 214 C215 218 ...

Page 141: ... RV8 ANALOG V1 00 1 00 U39 355 14761 ICSM DAC AK4395 24BIT VSOP 5 00 U58 62 355 15677 ICSM ADC PCM1804 24b 192kHz SO 4 00 U81 84 410 11639 RELAY 2P2T DIP 5V HI SENS 8 00 RY1 8 510 03961 CONN POST 100X025 HDR 2MCG 1 00 W1 510 13149 CONN RCA PCRA 1FCGX2V WH RED G 15 00 J1 15 510 14079 CONN POST 156X045 HDR 4MC LOK 1 00 J19 510 15687 CONN FFC 1 25MM 13 POS VERT 1 00 J24 510 15688 CONN FFC 1 25MM 16 P...

Page 142: ...HIN 1 1 10W 280K OHM 3 00 R130 214 298 203 16244 RESSM THIN 1 1 10W 33 2K OHM 9 00 R132 135 146 216 219 R230 300 303 314 203 16245 RESSM THIN 1 1 10W 47 5 OHM 3 00 R96 180 264 203 16249 RESSM THIN 1 1 10W 750 0 OHM 9 00 R97 108 139 181 192 R223 265 276 307 203 16250 RESSM THIN 1 1 10W 75 0 OHM 3 00 R106 190 274 203 16251 RESSM THIN 1 1 10W 95 3 OHM 12 00 R104 105 114 115 188 R189 198 199 272 273 R...

Page 143: ... 16203 DIODESM RECT 400V 50A 50NS SMB 6 00 D37 38 60 61 83 84 300 16205 DIODESM SW 250V 625mA MELF 6 00 D28 33 51 56 74 79 310 10510 TRANSISTORSM 2N3904 SOT23 9 00 Q27 35 46 54 65 73 Q84 88 92 310 10565 TRANSISTORSM 2N3906 SOT23 6 00 Q34 53 72 83 87 91 310 16206 TRANSISTORSM NPN 25V 225mW SOT 3 00 Q81 85 89 310 16207 TRANSISTORSM NPN 300V 1W SOT 3 00 Q22 41 60 310 16208 TRANSISTORSM PNP 50V 350mW ...

Page 144: ...03 11732 RESSM RO 1 1 10W 1 82K OHM 4 00 R359 370 381 392 203 11980 RESSM THIN 1 1 10W 10 0K OHM 12 00 R53 78 79 137 162 R163 221 246 247 R305 330 331 203 12722 RESSM THIN 1 1 10W 49 9K OHM 4 00 R54 138 222 306 203 13134 RESSM THIN 1 1 10W 1 00K OHM 11 00 R8 32 81 144 155 165 R228 231 312 315 333 203 13638 RESSM THIN 1 1 10W 2 49K OHM 20 00 R2 4 7 9 66 86 88 R91 93 150 170 172 R175 177 234 254 R25...

Page 145: ... 00 C82 121 240 16261 CAPSM ELEC 10uF 50V 20 4 00 C25 64 103 142 240 16262 CAPSM ELEC 4 7uF 16V NPOL 20 8 00 C157 158 161 162 C165 166 169 170 240 16263 CAPSM ELEC 33uF 16V NPOL 20 4 00 C2 41 80 119 244 16265 CAP MYL 0047uF 250V RAD 5 4 00 C29 68 107 146 244 16266 CAP MYL 01uF 250V RAD 5 8 00 C26 28 65 67 104 C106 143 145 244 16267 CAP MYL 33uF 63V RAD 10 4 00 C27 66 105 144 245 10416 CAPSM CER 10...

Page 146: ...63 76 310 16274 TRANSISTOR MJE15032 NPN TO220 4 00 Q7 26 45 64 310 16275 TRANSISTOR MJE15033 PNP TO220 4 00 Q11 14 330 15667 ICSM DIGITAL 74HCT594 SOIC 1 00 U30 330 16215 ICSM DIGITAL 74HCT597 SOIC 1 00 U50 340 10552 ICSM LIN MC33078 DU OPAMP SOIC 4 00 U1 5 9 13 340 11045 ICSM LIN LM393 DUAL COMP SOIC 4 00 U3 7 11 15 340 11948 ICSM LIN LM339 QUAD COMP SOIC 4 00 U4 8 12 16 340 16219 ICSM LIN TLE203...

Page 147: ...10W 680K OHM 1 00 R245 202 10948 RESSM RO 5 1 10W 390 OHM 1 00 R252 202 10949 RESSM RO 5 1 10W 1 2K OHM 1 00 R76 202 11042 RESSM RO 5 1 10W 6 8K OHM 4 00 R119 121 148 150 202 12369 RESSM RO 5 1 10W 36K OHM 6 00 R131 133 166 169 R202 207 202 13579 RESSM RO 5 1 10W 22 OHM 10 00 R31 36 41 46 50 R55 59 64 68 72 202 16144 RESSM RO 5 1 10W 12 OHM 1 00 R228 203 10560 RESSM RO 1 1 10W 75 0 OHM 32 00 R29 3...

Page 148: ... 00 C172 176 245 10561 CAPSM CER 100pF 50V COG 5 3 00 C64 169 174 245 10972 CAPSM CER 068uF 50V X7R 20 1 00 C180 245 10975 CAPSM CER 3300pF 50V X7R 10 1 00 C181 245 10976 CAPSM CER 47pF 50V COG 5 1 00 C117 245 10977 CAPSM CER 330pF 50V COG 5 1 00 C173 245 11591 CAPSM CER 560pF 50V COG 5 3 00 C27 29 34 245 11625 CAPSM CER 33pF 50V COG 5 1 00 C109 245 12070 CAPSM CER 15pF 50V COG 10 1 00 C100 245 12...

Page 149: ...R 4MC LOK 1 00 J18 510 15471 CONN RCA PCRA 1FCGX2V GRN GND 2 00 J7 10 510 15472 CONN RCA PCRA 1FCGX2V RED GND 2 00 J5 8 510 15473 CONN RCA PCRA 1FCGX2V BLU GND 2 00 J6 9 510 15688 CONN FFC 1 25MM 16 POS VERT 1 00 J20 640 01701 SCRW 4 40X1 4 PNH PH ZN 1 00 U32 704 06165 HEATSINK TO220 75X 5X 5 TAB 1 00 U24 704 09508 HEATSINK TO220 MTTAB W 4 40NUT 1 00 U32 710 15580 PC BD VIDEO RV8 1 00 PICK REV 4 P...

Page 150: ...227 CONN 163 HDR 2MC SHR POL LK 1 00 J21 510 16228 CONN 250 HDR 2X3MCG SHR POL 3 00 J4 14 15 510 16278 CONN 163 HDR 2X3MC SHR POL L 2 00 J2 5 525 16281 TERM QDC 250 PC 2LS LK 1 00 J12 525 16282 TERM QDC 250 PCRA 2LS 2 00 J6 7 600 16230 FUSE CLIP 3AG 5X20MM PC 2 00 HW1 2 710 16170 PC BD PS RV8 1 00 PICK REV 2 PC BOARD 740 11287 LABEL S N PCB PRINTED 1 00 PLACE OVER HW4 Chassis Assembly 022 15610 PL...

Page 151: ...ZN 8 00 ACCESS PLATE TO CHAS 641 11466 SCRW TAP 4X3 8 PNH PH BZ TRI 20 00 RCA CONN TO R PNL ALIGN HOLES W CONNS BEFORE TORQUING SCREWS 643 10492 NUT M4X 7MM KEP ZN 1 00 CHASSIS GND 644 01741 WSHR INT STAR 8 ZN 4 00 REAR HANDLES 644 01747 WSHR INT STAR 4 ZN 4 00 DSUB JSCKT 644 10494 WSHR FL M4CLX9ODX 8MM THK 1 00 CHASSIS GND 680 15630 WIRE 14G G Y 3 5 187QDCRA LUG8 1 00 AC IN TO CHASSIS GND 680 156...

Page 152: ...TO FP 640 10495 SCRW M3X12MM PNH PH ZN 1 00 IR ENC BD 640 10498 SCRW M3X6MM PNH PH BZ 10 00 SHIELD TO FP 640 10498 SCRW M3X6MM PNH PH BZ 11 00 SW LED BD TO FP 640 10498 SCRW M3X6MM PNH PH BZ 2 00 HEADPHONE BRKT 640 15476 SCRW M4X8MM PNH PH ZN 6 00 SPT BRKTS TO FP 680 14693 CABLE 100 PLUG SCKT 2X7C 10 5 1 00 SOLDER TO DSPLY DSPLY TO SW LED BD 701 14858 SHIELD 6 7X1 8X 4 H 1 00 701 15454 BRACKET SUP...

Page 153: ...DGE RECT RV8 1 00 VCO Mechanical Assembly 023 16129 PL VCO BD ASSY MCLK 1 00 700 14838 HOUSING VCO MC12 1 00 700 14839 COVER VCO MC12 1 00 3 Channel Amp Bd Mechanical Assembly 022 16446 PL HS ASSY SGL POS RV8 1 00 022 16447 PL HS ASSY SGL NEG RV8 1 00 022 16448 PL HS ASSY DBL POS RV8 1 00 022 16449 PL HS ASSY DBL NEG RV8 1 00 023 15824 PL AMP BD ASSY 3CH RV8 1 00 023 15890 PL SPKR EMI FILTER BD AS...

Page 154: ... MJ21193 PNP TO3 2 00 630 16421 INSUL SIL RUB 94X 66 1 00 641 16289 SCRW TAP 6 32X 25 PNH TORX ZN 4 00 704 16431 HEATSINK AMP SGL RV8 1 00 Double Positive Heatsink Assembly 100 01759 CHEM HEATSINK COMP SILICONE 0 003 oz 310 16276 TRANSISTOR MJ21194 NPN TO3 4 00 630 16421 INSUL SIL RUB 94X 66 2 00 641 16289 SCRW TAP 6 32X 25 PNH TORX ZN 8 00 704 16432 HEATSINK AMP DBL RV8 1 00 Double Negative Heats...

Page 155: ... F 1 5M L 1 00 480 15842 ANTENNA FM PAL 1 5M L 1 00 560 16125 ADPTR RF CONN F MALE PAL MALE 1 00 730 15818 BOX 26 75X23 375X15 25 BLANK 1 00 OUTER BOX 730 15819 BOX 25 875X22 5X14 LEXICON 1 00 INNER BOX 730 15821 INSERT FOAM BASE 4UX19 1 00 730 15822 INSERT FOAM TOP 4UX19 1 00 730 15823 BOX 18 75X12 625X2 5 1 00 730 15829 TRAY ACCESSORY RV8 1 00 ...

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Page 186: ...ND CHASSIS ANALOG GROUND DIGITAL NOTES 1 060 13699 CW 10 27 99 10 27 99 KB RWH KB KB 4 10 00 CW 4 28 00 SCHEM IR ENC BD MC12 1 CHANGED PER DCR 000327 00 3 27 00 RWH 2 CHANGED PER DCR 000925 01 10 13 00 CW 10 20 00 OVERLOAD IR ACK 1 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V 2 3 LAST REFERENCE DESIGNATORS USED C2 D4 J1 R3 SW1 U1 4 INSTALL ONE ONLY OF U1A B C 3 3 CHANGED R3 FROM 2 4K TO 1 5K PER...

Page 187: ...Inc 0 SCHEM EXP TEST BD RV8 6 COMPONENTS MARKED WITH ARE NOT ON BOM SPARE 1 2 EXPANSION SLOT B 2 3 EXPANSION SLOT A 4 29 03 RWH CW 4 29 03 5 2 03 KAB CAM 4 29 03 RWH CAM 4 29 03 CW 4 29 03 KAB 5 2 03 5 LAST REFERENCE DESIGNATORS USED C2 FB1 J3 R1 RP2 U2 W1 15379 0 5 5 2003_15 43 1 1 1 EXP_RESET EXPCS0 EXPCS1 EXPI7 EXPI6 EXPI5 EXPI4 EXPI3 EXPI2 EXPI1 EXPI0 EXPI0 EXPI7 EXPI6 EXPI5 EXPI4 EXPI3 EXPI2 ...

Page 188: ... CONNECTOR GROUND POWER 4 GROUND GROUND CHASSIS ANALOG GROUND DIGITAL 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V 2 1 4 CVID COMPOSITE VIDEO INPUTS NOTES 3 5 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W 1 2002 Lexicon Inc RCA INPUTS 060 15509 SCHEM VIDEO IN BD RV8 5 LAST REFERENCE DESIGNATORS USED C12 J6 Q5 R15 0 9 3 2002_11 12 1 15509 0 1 CVID...

Page 189: ...exicon REV 3 OAK PARK BEDFORD MA 01730 YEL RCA ZONE2 OUT COMPOSITE VIDEO OUT COMPOSITE VIDEO 1 NOTES 1 2002 Lexicon Inc SCHEM VIDEO OUT BD RV8 1 LAST REFERENCE DESIGNATORS USED J5 060 15519 RCA OUTPUTS MAIN 2 1 2 1 OSD VIDEO BOARD CONNECTOR 0 15519 0 9 3 2002_11 25 1 CVID_ZON22 CVID_MAIN1 CVID_MAIN2 CVID_ZON21 2 3 4 5 6 7 8 9 10 11 13 14 12 1 J5 1 2 J1 2 1 J2 1 2 J4 2 1 J3 8 7 02 CW ECM RWH MAG 8 ...

Page 190: ...ITORS ARE UF V 060 15529 PHONO PREAMP ANALOG BOARD CONNECTOR TO PHONO PREAMP MIC INPUTS RWH 8 15 02 DOCUMENT CONTROL BLOCK 060 15529 SCHEM MIC PREAMP BD RV8 CW CHANGED PER DCR 021030 00 11 20 02 CBV MAG 11 26 02 11 26 02 2 2003 Lexicon Inc 2 2 RWH 7 COMPONENTS MARKED WITH ARE NOT ON BOM INSTALLED ONLY 6 LAST REFERENCE DESIGNATORS USED C46 D14 FB8 J4 LUG1 R55 U5 FOR WHITE OVER RED RCA CONNECTOR RWH...

Page 191: ...A 15VA 15VA 1 25 1 25 LM317M VIN ADJ VOUT CASE VOUT 1 25 22 16 BAV99 15VA MC33078 MC33078 MC33078 MC33078 MAG 5 22 03 5 22 03 CW CBV 5 22 03 RWH 11 20 02 CBV RWH MAG 11 26 02 11 26 02 060 15529 MIC INPUTS MICROPHONE BIAS VOLTAGE SUPPLY MIC IN 2 MIC IN 1 SCHEM MIC PREAMP BD RV8 RWH 8 15 02 CBV CW MAG 8 16 02 8 26 02 8 15 02 1 CHANGED PER DCR 021030 00 11 27 02 CW 2 CHANGED PER DCR 030317 00 2 5 21 ...

Page 192: ...ALOG GROUND DIGITAL NOTES HEADPHONE OUTPUT 1 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V SCHEM HEADPHONE BD RV8 2 4 COMPONENTS MARKED WITH ARE NOT ON BOM CW 8 26 02 CBV 8 26 02 RWH 8 27 02 8 27 02 MAG CHANGED PER DCR 021029 00 060 15539 11 4 02 CW CBV 11 12 02 RWH 11 14 02 MAG 11 14 02 2 2003 Lexicon Inc 3 LAST REFERENCE DESIGNATORS USED C2 FB3 J2 2 CHANGED PER DCR 030515 00 RWH 5 22 03 ECM 5 2...

Page 193: ...0K 1 4 15 03 4 15 03 GROUND POWER 4 GROUND GROUND CHASSIS ANALOG GROUND DIGITAL NOTES 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V 060 15549 12 3 02 12 9 02 RWH CW MAG 12 9 02 CAM 12 4 02 6 COMPONENTS MARKED WITH ARE NOT ON BOM 2003 Lexicon Inc 1 1 5 LAST REFERENCE DESIGNATORS USED C21 FB1 J2 L1 R16 U...

Page 194: ...2 00 2004 HSG 4 27 04 RWH 5 2 04 KAB 4 29 04 CW CAM 4 29 04 19 19 19 1 1 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 5 6 2004_9 30 19 15559 6 SPARE_AD 12 A8 TEMP7 TEMP4 12 B8 TEMP 7 1 TEMP3 TEMP2 TEMP1 TEMP6 TEMP5 1 2 3 W4 W3 1 2 3 W5 R82 BOOTCS PROGCS CPUCS2 2 C7 9 C8 CPUCS3 7 B5 ROMUCS 8 1 RP13 6 3 RP13 R117 10K E6 R127 0 ADDR19 ADDR20 R84 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 10 4...

Page 195: ... FP_RESET 12 B6 D12 D11 D10 MAINS_RLY 12 A4 CPUCS2 1 B3 9 C8 2 3 4 5 6 7 8 9 17 16 15 14 13 12 11 19 1 18 20 10 U37 20 10 18 2 3 15 12 5 6 9 16 19 4 7 8 13 14 17 11 1 U21 1 11 17 14 13 8 7 4 19 16 9 6 5 12 15 3 2 18 10 20 U20 CPU_TEST_LED1 CPU_TEST_LED 6 1 CPU_TEST_LED1 CPU_TEST_LED2 CPU_TEST_LED3 CPU_TEST_LED4 CPU_TEST_LED6 CPU_TEST_LED5 CPU_TEST_LED6 CPU_TEST_LED5 CPU_TEST_LED4 CPU_TEST_LED3 CPU...

Page 196: ...2 2 03 ECM 10 9 03 MAG 10 9 03 CAM 10 2 03 CHANGED PER DCR 030626 00 RWH 9 29 03 MAG 5 20 03 5 20 03 CW 5 2 03 RWH CAM 5 14 03 2 CHANGED PER DCR 030307 00 MAG 12 20 02 12 20 02 CW 11 06 02 CAM 11 05 02 RWH 1 CHANGED PER DCR 020913 00 RWH CAM CW JV 4 30 02 5 1 02 4 30 02 4 26 02 SCHEM MAIN BD RV8 060 15559 MODULATION 3 75 DSP HOST 1 AND 2 MODULATION 1 25 SPARES 3 4 4 3 19 15559 6 5 6 2004_9 30 3 W1...

Page 197: ...AM CW JV 4 30 02 5 1 02 4 30 02 4 26 02 CHIP SELECT FOR EEPROM 1 1 0 1 0 0 0 1 0 1 1 0 1 X BMS BECOMES AN OUTPUT DSP A SDRAM AND FLASH 060 15559 SCHEM MAIN BD RV8 EBOOT LBOOT BMS STATE HOST BOOT N A SPI BOOT DEFAULT LINK PORT BOOT EEPROM BOOT N A RESERVED 3 3 4 5 6 2004_9 30 15559 6 4 19 DSPA_AD10 6 3 RP4 2 7 RP4 8 1 RP4 25 26 24 27 60 61 62 63 64 65 66 22 23 67 68 2 4 77 79 80 82 83 85 31 33 34 3...

Page 198: ...V 4 30 02 5 1 02 4 30 02 4 26 02 060 15559 SCHEM MAIN BD RV8 CHIP SELECT FOR EEPROM 1 1 0 1 0 0 0 1 0 1 1 0 1 X BMS BECOMES AN OUTPUT DSP B EXTERNAL MEMORY SPARES EBOOT LBOOT BMS HOST BOOT N A SPI BOOT DEFAULT LINK PORT BOOT EEPROM BOOT N A RESERVED 3 3 5 19 5 6 2004_9 30 15559 6 5 NC 5 4 RP12 DSPB_A 14 0 DSPB_A14 DSPB_A14 DSPB_A13 DSPB_A0 DSPB_A9 DSPB_A4 DSPB_A1 DSPB_A2 DSPB_A9 DSPB_A8 DSPB_A7 DS...

Page 199: ...M 11 05 02 RWH 1 CHANGED PER DCR 020913 00 RWH CAM CW JV 4 30 02 5 1 02 4 30 02 4 26 02 SCHEM MAIN BD RV8 060 15559 DSP SPI SERIAL AND LINK PORTS 3 3 6 19 15559 6 5 6 2004_9 30 6 R74 10K DSPBSP3FPGA 9 B8 DSPASP0FPGA 9 C8 R140 10K 8 C8 9 C2 DSPATXD 8 C8 9 C2 DSPARXD 8 C8 9 C2 DSPASPICLK SPORT_CLK_B 9 B8 DSPB2DSPA DSPA2DSPB DSPABLDATA7 DSPABLDATA6 DSPABLDATA5 DSPABLDATA4 DSPABLDATA3 DSPABLDATA2 DSPA...

Page 200: ... A8 B1 B2 B3 B4 B5 B6 B7 B8 DIR GND VCC G 74VHCT245 5VD 1A 5 2 04 KAB 4 29 04 CW CAM 4 29 04 4 27 04 RWH ECM 10 9 03 MAG 10 9 03 CAM 10 2 03 CHANGED PER DCR 030626 00 RWH 9 29 03 MAG 5 20 03 5 20 03 CW 5 2 03 RWH CAM 5 14 03 2 CHANGED PER DCR 030307 00 MAG 12 20 02 12 20 02 CW 11 06 02 CAM 11 05 02 RWH 1 CHANGED PER DCR 020913 00 RWH CAM CW JV 4 30 02 5 1 02 4 30 02 4 26 02 060 15559 1 8V 1 8V SCH...

Page 201: ... 00 RWH 9 29 03 MAG 5 20 03 5 20 03 CW 5 2 03 RWH CAM 5 14 03 2 CHANGED PER DCR 030307 00 MAG 12 20 02 12 20 02 CW 11 06 02 CAM 11 05 02 RWH 1 CHANGED PER DCR 020913 00 RWH CAM CW JV 4 30 02 5 1 02 4 30 02 4 26 02 060 15559 SCHEM MAIN BD RV8 CRYSTAL DSP SPARES 3 3 8 19 8 15559 6 10 10 2003_11 04 CRY_SPICLK 9 C2 SPICLK 9 C2 CRY_SCS 2 C3 CRY_RESET SCS CRST 6 D6 9 C2 DSPASPICLK DSPARXD 6 D6 9 C2 DSPA...

Page 202: ...N2 MAIN_I2S_IN1 MAIN_I2S_IN3 CPUADDR 20 0 1 D3 7 B5 CPUADDR6 CPUADDR5 CPUADDR4 CPUADDR3 CPUADDR2 CPUADDR1 CPUADDR0 CPUADDR8 CPUADDR9 CPUADDR7 CPUCS2 1 B3 2 C7 CPUWRL 1 B3 7 B5 CPURD 1 B3 7 B5 CPUCLKOUT 1 D8 FPGA_RESET 2 B4 WRDCLKMON 2 D3 5 4 RP25 47 1 8 47 RP25 3 6 47 RP25 7 2 RP25 47 3 6 47 RP26 5 4 RP26 47 8 1 47 RP27 5 4 RP27 47 3 6 47 RP27 7 2 RP27 47 DATA_LATCHB 12 B8 12 D4 ADA_LATCH ADA_SCLK...

Page 203: ...MING PORT FPGA DONE LED SPARES FPGA FLASH PROM for development only FPGA FLASH 3 3 10 19 10 10 10 2003_11 04 15559 6 AUDIO_OSC 9 A8 R147 1 2 3 4 5 6 7 8 9 J16 EXPA0 EXPA17 EXPA16 EXPA12 EXPA11 EXPA8 EXPA3 EXPA7 EXPA15 11 D4 EXPA 17 0 EXPA4 EXPA1 EXPA2 EXPA9 EXPA6 EXPA5 EXPA10 EXPA13 EXPA14 2 35 4 33 15 31 20 25 13 9 23 11 1 6 7 8 10 17 18 26 28 29 30 36 38 39 40 43 14 3 12 24 34 16 27 19 21 5 41 4...

Page 204: ... 1 8 47 RP33 2 7 47 RP33 4 5 47 RP33 3 6 47 RP33 1 8 47 RP34 2 7 47 RP34 4 5 47 RP34 3 6 47 RP34 1 8 47 RP35 2 7 47 RP35 4 5 47 RP35 3 6 47 RP35 1 8 47 RP36 4 5 47 RP36 2 7 47 RP36 3 6 47 RP36 1 8 47 RP37 2 7 47 RP37 4 5 47 RP37 3 6 47 RP37 3 6 RP29 47 2 7 RP29 47 4 5 RP29 47 1 8 RP29 47 1 8 RP30 47 2 7 RP30 47 4 5 RP30 47 3 6 RP30 47 1 8 RP31 47 2 7 RP31 47 4 5 RP31 47 3 6 RP31 47 1 8 RP32 47 2 7...

Page 205: ... J4 9 8 7 6 5 40 4 39 38 37 36 35 34 33 32 31 30 3 29 28 27 26 25 24 23 22 21 20 2 19 18 17 16 15 14 13 12 11 10 1 J26 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 5 6 7 8 9 J20 1 C8 BROWN_OUT 2 D3 MAINS_RLY R172 R21 DISP_E 7 B3 DISP_RW 7 B3 SOFT_RLY 2 D3 REC_DAC_MCKI 9 B2 9 B2 MAIN_FS64 9 B2 REC_ADC_FS64 CVID_ZON3 13 B3 SYNC_DETECT 9 B2 VIDE...

Page 206: ...AM 10 2 03 CHANGED PER DCR 030626 00 RWH 9 29 03 MAG 5 20 03 5 20 03 CW 5 2 03 RWH CAM 5 14 03 2 CHANGED PER DCR 030307 00 MAG 12 20 02 12 20 02 CW 11 06 02 CAM 11 05 02 RWH 1 CHANGED PER DCR 020913 00 RWH CAM CW JV 4 30 02 5 1 02 4 30 02 4 26 02 060 15559 SCHEM MAIN BD RV8 SPDIF_I O S PDIF RECORD OUTPUTS SPARES 3 3 13 19 10 10 2003_11 04 13 15559 6 SPDIF_COAX_IN4 SPDIF_COAX_IN 4 1 9 C7 SPDIF_COAX...

Page 207: ...T VOUT GND ADJ VIN ON OFF CASE GND 74VHC04 ECM 10 9 03 MAG 10 9 03 CAM 10 2 03 CHANGED PER DCR 030626 00 RWH 9 29 03 MAG 5 20 03 5 20 03 CW 5 2 03 RWH CAM 5 14 03 2 CHANGED PER DCR 030307 00 MAG 12 20 02 12 20 02 CW 11 06 02 CAM 11 05 02 RWH 12V 1 CHANGED PER DCR 020913 00 SPARES RWH CAM CW JV 4 30 02 5 1 02 4 30 02 4 26 02 060 15559 SCHEM MAIN BD RV8 REMOTE POWER CONTROL DRIVERS TRIGGER OUTPUTS 1...

Page 208: ...3 MAG 5 20 03 5 20 03 CW 5 2 03 RWH CAM 5 14 03 2 CHANGED PER DCR 030307 00 MAG 12 20 02 12 20 02 CW 11 06 02 CAM 11 05 02 RWH 1 CHANGED PER DCR 020913 00 RWH CAM CW JV 4 30 02 5 1 02 4 30 02 4 26 02 060 15559 SCHEM MAIN BD RV8 SPARES VCO MODULE 44 1K AND 48K 512FS VCO A 88 2K AND 96K 256 FS 3 3 15 19 15559 6 4 27 2004_9 56 15 9 A8 MAIN_PLL_MCKO NC 5 6 U10 NC 3 4 U10 PLL_OUTA R43 47 VCOA_5V 7 14 2...

Page 209: ... MAG 5 20 03 5 20 03 CW 5 2 03 RWH CAM 5 14 03 2 CHANGED PER DCR 030307 00 MAG 12 20 02 12 20 02 CW 11 06 02 CAM 11 05 02 RWH 1 CHANGED PER DCR 020913 00 RWH CAM CW JV 4 30 02 5 1 02 4 30 02 4 26 02 VCO B 060 15559 SCHEM MAIN BD RV8 SPARES VCO MODULE 44 1K AND 48K 512FS 88 2K AND 96K 256 FS 3 3 16 4 27 2004_9 56 15559 6 19 16 C93 C59 R92 NC 9 A8 ZONE2_PLL_MCKO C88 NC 8 9 U23 VCOB_5V PLL_OUTB C83 8...

Page 210: ...1N4002 3 3VD 2 1 2 1 2 1 2 5VD 1 2 3 4 ECM 10 9 03 MAG 10 9 03 CAM 10 2 03 RWH MAG 5 20 03 5 20 03 CW 5 2 03 RWH CAM 5 14 03 2 CHANGED PER DCR 030307 00 MAG 12 20 02 12 20 02 CW 11 06 02 CAM 11 05 02 RWH 1 CHANGED PER DCR 020913 00 RWH CAM CW JV 4 30 02 5 1 02 4 30 02 4 26 02 060 15559 SCHEM MAIN BD RV8 POWER CONNECTOR POWER SUPPLY 2 5V REGULATOR FAN CONNECTORS 3 3V REGULATOR 3 CHANGED PER DCR 030...

Page 211: ...1 SHIELD ECM 10 9 03 MAG 10 9 03 CAM 10 2 03 RWH CHANGED PER DCR 030626 00 MAG 5 20 03 5 20 03 CW 5 2 03 RWH CAM 5 14 03 2 CHANGED PER DCR 030307 00 MAG 12 20 02 12 20 02 CW 11 06 02 CAM 11 05 02 RWH 1 CHANGED PER DCR 020913 00 RWH CAM CW JV 4 30 02 5 1 02 4 30 02 4 26 02 SCHEM MAIN BD RV8 060 15559 REAR PANEL IR INPUT IR REMOTE CONNECTOR 3 3 9 29 03 19 18 18 10 10 2003_11 04 15559 6 4 5 1 3 2 U1 ...

Page 212: ... 25 1 25 001 50 001 50 01 25 01 25 1 25 1 25 1 25 1 25 5 2 04 KAB 4 29 04 CW CAM 4 29 04 4 27 04 RWH ECM 10 9 03 MAG 10 9 03 CAM 10 2 03 CHANGED PER DCR 030626 00 RWH 9 29 03 MAG 5 20 03 5 20 03 CW 5 2 03 RWH CAM 5 14 03 2 CHANGED PER DCR 030307 00 MAG 12 20 02 12 20 02 CW 11 06 02 CAM 11 05 02 RWH 1 CHANGED PER DCR 020913 00 1 8V B RWH CAM CW JV 4 30 02 5 1 02 4 30 02 4 26 02 SCHEM MAIN BD RV8 06...

Page 213: ... MAIN BD CONNECTORS 1 7 COMPONENTS MARKED WITH ARE NOT ON BOM CHANGED PER DCR 021028 00 FLEX RIBBON 11 4 02 CW RWH 11 6 02 11 5 02 MAG 11 6 02 2 3 24 03 3 27 03 CAM 3 26 03 3 25 03 3 3 3 CHANGED SHEET 4 PER DCR 030320 00 2 3 RWH 9 19 03 6 LAST REFERENCE DESIGNATORS USED C15 D40 J5 Q4 R51 RP4 2003 HSG CHANGED SHEETS 2 4 PER DCR 030821 00 1 11 20 2003_17 06 15569 3 1 1 10 11 12 13 14 15 16 17 18 19 ...

Page 214: ...ECM MAG 7 8 02 RED BLK YEL VIO WHT GRN VCC GND TCK TDO TDI TMS 060 15569 4 JTAG PROGRAMMING PORT FRONT PANEL CPLD SCHEM SW LED BD RV8 2 9 19 03 2 ADDED JTAG RES PER DCR 030821 00 2 11 20 2003_17 07 15569 3 2 R32 R34 R33 SROW_ 15 0 1 B5 3 B7 SROW_14 SROW_13 SROW_12 SROW_11 SROW_10 SROW_9 SROW_8 SROW_7 SROW_6 SROW_5 SROW_4 SROW_3 SROW_2 SROW_1 SROW_0 SROW_15 21 31 44 62 69 75 84 100 77 87 92 94 91 9...

Page 215: ...ROW_14 SROW_15 SROW_15 SROW_7 SROW_5 SROW_5 SROW_4 SROW_4 SROW_3 SROW_2 SROW_1 SROW_1 SROW_0 SROW_0 SROW_2 SROW_3 SROW_7 1 B5 2 B4 SROW_ 15 0 SROW_12 SROW_12 SROW_11 SROW_10 SROW_9 SROW_8 SROW_8 SROW_9 SROW_10 SROW_11 SROW_13 SROW_13 SROW_7 SROW_7 SROW_6 SROW_4 SROW_4 SROW_3 SROW_3 SROW_2 SROW_2 SROW_1 SROW_0 SROW_0 SROW_1 SROW_5 SROW_5 SROW_6 SROW_15 SROW_14 SROW_13 SROW_12 SROW_11 SROW_10 SROW_9...

Page 216: ...DVD1 Z3DVD1 MOFF MUTE AMP1 STDBY READY AMP2 AMP3 AMP4 AMP7 AMP6 AMP5 Z3OFF FRONT PANEL LED MATRIX SCHEM SW LED BD RV8 Z2OFF Z2SAT Z2DVD2 Z2TUNER Z2AUX Z2CD Z2TV Z2VCR Z3AUX Z3TUNER Z3CD Z3TV Z3VCR Z3SAT Z3DVD2 BYPASS CAPACITORS CHANGED PER DCR 021028 00 3 2 PER DCR 030320 00 CHANGED LED COLOR SCHEME 3 24 03 CW 3 CHANGED RESISTORS PER DCR 030821 00 9 19 03 RWH 9 26 03 KB 11 17 03 CW CAM 9 23 03 4 1...

Page 217: ...O BD RV8 8 7 6 5 4 3 2 1 LEFT ANALOG INPUTS 7 COMPONENTS MARKED WITH ARE NOT ON BOM REC SOURCE SELECT LEFT MAIN SOURCE SELECT LEFT ZONE SOURCE SELECT LEFT CENTER UNITY GAIN PASS THRU LEFT SIDE UNITY GAIN PASS THRU LEFT ANALOG INPUT MUXES RWH CBV CW MAG 8 29 02 8 29 02 8 28 02 8 27 02 MAG 11 21 02 11 20 02 CW CBV 11 20 02 CONTROL REGISTERS BYPASS CAPACITORS 1 CHANGED PER DCR 021107 00 11 14 02 RWH ...

Page 218: ...R DCR 021107 00 RWH RWH CBV CW MAG 8 29 02 8 29 02 8 28 02 8 27 02 1 2 3 4 5 6 7 8 0dBFS 4 0Vrms 060 15579 SCHEM ANALOG I O BD RV8 RIGHT ANALOG INPUTS RIGHT ANALOG INPUT MUXES RIGHT SIDE UNITY GAIN PASS THRU SUB UNITY GAIN PASS THRU ZONE SOURCE SELECT RIGHT REC SOURCE SELECT RIGHT MAIN SOURCE SELECT RIGHT 11 14 02 3 3 9 29 03 2 15579 6 10 7 2003_11 05 17 2 5 6 7 8 4 U3 2 16 12 11 10 9 6 7 5 1 15 4...

Page 219: ...H CBV CW MAG 8 29 02 8 29 02 8 28 02 8 27 02 060 15579 SCHEM ANALOG I O BD RV8 R PHONO INPUT L PHONO INPUT L PHONO 75U INPUT R PHONO 75U INPUT L MIC INPUT 1 R MIC INPUT 2 L TUNER INPUT R TUNER INPUT MORE ANALOG INPUT MUXES REC SOURCE SELECT MAIN SOURCE SELECT 11 14 02 ZONE SOURCE SELECT 3 3 9 29 03 3 15579 6 10 7 2003_11 05 17 3 4 8 1 3 2 U88 4 8 7 5 6 U88 4 8 1 3 2 U89 4 8 7 5 6 U89 4 8 1 3 2 U86...

Page 220: ...EM ANALOG I O BD RV8 MIC INPUT MAIN A D CONVERTER PHONO 75U INPUT INPUTS MAIN A D CONVERTER 0dBFS 2 0Vrms 11 14 02 3 3 9 29 03 10 7 2003_11 05 4 15579 6 4 17 C367 4 A8 10 B5 RIGHT_MAIN_IN_LVL R354 R355 5 6 7 8 4 U71 3 2 1 8 4 U71 R339 MAIN_PHONO75_SEL 14 D3 ADA_SDATA_OUT 8 C7 10 C7 11 C7 12 C7 13 C7 14 B5 15 A5 15 C5 5 D5 6 D4 7 B7 8 B6 9 B6 10 C7 11 C7 12 C7 13 C7 14 B5 15 C5 ADA_SCLK RIGHT_MAIN_...

Page 221: ... CBV CW MAG 8 29 02 8 29 02 8 28 02 8 27 02 7dB 0dBFS 0 884Vrms 060 15579 0dBFS 2 0Vrms SCHEM ANALOG I O BD RV8 C SUB A D CONVERTER INPUTS C SUB A D CONVERTER CENTER SUB DIRECT INPUT 11 14 02 3 3 9 29 03 5 15579 6 5 10 7 2003_11 05 17 CENTER_IN 1 B3 2 B3 SUB_IN R347 R346 5 6 7 8 4 U55 3 2 1 8 4 U55 4 8 6 5 7 U69 4 8 2 3 1 U69 VC_MUTE 4 C5 6 C4 7 A7 8 B7 9 C7 9 B7 14 B3 MAIN_VC_ZCEN 4 C5 6 C4 7 A7 ...

Page 222: ...W MAG 8 29 02 8 29 02 8 28 02 8 27 02 0dBFS 2 0Vrms 0dBFS 0 884Vrms 060 15579 7dB SCHEM ANALOG I O BD RV8 SIDE A D CONVERTER MIC INPUT INPUTS SIDE A D CONVERTER 11 14 02 3 9 29 03 4 17 2 2 2004_11 13 6 15579 6 6 LEFT_SIDE_IN_LVL 6 D2 12 D5 RIGHT_SIDE_IN_LVL 6 C2 12 B5 R350 R351 LEFT_SIDE_IN_HALF 9 D7 9 C7 RIGHT_SIDE_IN_HALF 5 6 7 8 4 U56 3 2 1 8 4 U56 5 6 7 8 4 U70 3 2 1 8 4 U70 R352 6 B8 12 D5 LE...

Page 223: ...02 8 28 02 8 27 02 7dB 0dBFS 2 0Vrms 0dBFS 0 884Vrms 0dBFS 2 0Vrms 060 15579 SCHEM ANALOG I O BD RV8 REC INPUT LEVEL CONTROL REC A D CONVERTER REC_DAC_OUT MIC INPUT PHONO 75U INPUT REC A D CONVERTER 11 14 02 3 3 9 29 03 17 7 10 7 2003_11 05 7 15579 6 8 B7 VC_3 100K R264 R343 R342 7 B7 LEFT_REC_IN_HALF RIGHT_REC_IN_HALF 7 A7 5 6 7 8 4 U54 3 2 1 8 4 U54 5 6 7 8 4 U68 3 2 1 8 4 U68 14 B3 REC_ADC_RST ...

Page 224: ... O BD RV8 REC DAC OUT LEVELS ZONE2 LEFT ZONE2 RIGHT OUT VAR ZONE2 LEFT ZONE2 RIGHT OUT FIX 0dBFS 4Vrms 0dBFS 4Vrms 11 14 02 6 7dB REC D A CONVERSION LEVEL CONTROL REC OUTPUT 0dBFS 1 98Vrms 0dBFS 4 3Vrms 3 3 9 29 03 8 17 10 7 2003_11 05 8 15579 6 ADA_SDATA_OUT 4 D5 10 C7 11 C7 12 C7 13 C7 14 B5 15 A5 15 C5 4 8 7 5 6 U52 4 8 1 3 2 U52 4 8 1 3 2 U32 4 8 7 5 6 U32 4 8 1 3 2 U13 R210 7 C8 8 B7 R_REC_DA...

Page 225: ... LEFT OUT ZONE3 RIGHT OUT SCHEM ANALOG I O BD RV8 ZONE OUTPUT LEVEL CONTROL REAR OUTPUT ZONE OUT LEVELS 0dBFS 4Vrms 11 14 02 0dBFS 4 3Vrms 3 3 9 29 03 15579 6 17 9 10 7 2003_11 05 9 4 8 7 5 6 U33 4 8 1 3 2 U33 4 D5 5 D5 6 D4 7 B7 8 B6 10 C7 11 C7 12 C7 13 C7 14 B5 15 C5 ADA_SCLK L_ZONE_DACOUT 9 D3 ZONE_RLY_CNTL 8 A4 C67 C68 15 A8 16 B8 R_ZONE_AMP L_ZONE_AMP 15 A8 16 C8 ZONE_DIRECT_SEL 14 C6 ZONE_D...

Page 226: ... 28 02 8 27 02 060 15579 SCHEM ANALOG I O BD RV8 LEFT RIGHT FRONT D A CONVERSION L R FRONT DACS 11 14 02 LEFT FRONT OUT RIGHT FRONT OUT 11 2dB 0dBFS 7 2Vrms 0dBFS 1 98Vrms 0dBFS 7Vrms 3 9 29 03 4 CHANGED PER DCR 031125 00 RWH 1 14 04 5 RWH ECO 040408 00 CHANGED R45 48 R99 100 PER 4 27 04 6 CHANGED U29 PER ECO 040526 00 15579 6 10 17 10 6 21 2004_14 22 10 5 9 11 13 12 4 U29 15 5 16 14 13 12 4 U29 7...

Page 227: ... 11 20 02 CW CBV 11 20 02 1 CHANGED PER DCR 021107 00 RWH RWH CBV CW MAG 8 29 02 8 29 02 8 28 02 8 27 02 060 15579 SCHEM ANALOG I O BD RV8 SUB OUT CENTER OUT CENTER SUB D A CONVERSION CENTER AND SUB DACS 11 2dB 11 14 02 0dBFS 7 2Vrms 0dBFS 1 98Vrms 0dBFS 7Vrms 3 9 29 03 ECO 040408 00 5 CHANGED R41 44 R96 97 PER RWH 4 27 04 CHANGED U27 PER ECO 040526 00 6 15579 6 11 6 21 2004_14 23 11 17 10 5 9 11 ...

Page 228: ...1 02 11 20 02 CW CBV 11 20 02 1 CHANGED PER DCR 021107 00 RWH RWH CBV CW MAG 8 29 02 8 29 02 8 28 02 8 27 02 060 15579 SCHEM ANALOG I O BD RV8 LEFT RIGHT SIDE D A CONVERSION L R SIDE DACS 11 2dB 11 14 02 RIGHT SIDE OUT LEFT SIDE OUT 0dBFS 7Vrms 0dBFS 1 98Vrms 0dBFS 7 2Vrms 3 9 29 03 CHANGED R37 40 R94 95 PER 4 27 04 CHANGED U25 PER ECO 040526 00 6 15579 6 17 12 6 21 2004_14 23 12 10 5 9 11 13 12 4...

Page 229: ...CR 021107 00 RWH CBV CW MAG 8 29 02 8 29 02 8 28 02 8 27 02 060 15579 SCHEM ANALOG I O BD RV8 LEFT REAR OUT RIGHT REAR OUT LEFT RIGHT REAR D A CONVERSION L R REAR DACS 11 2dB RWH 11 14 02 0dBFS 7Vrms 0dBFS 1 98Vrms 0dBFS 7 2Vrms 3 9 29 03 CHANGED R102 105 PER ECO 040421 00 5 CHANGED R33 36 R92 93 PER ECO 040408 00 RWH 4 27 04 6 6 CHANGED U24 PER ECO 040526 00 RWH 6 14 04 15579 6 6 21 2004_14 23 13...

Page 230: ...NO75_SEL 4 C8 MAIN_TUNER_SEL 3 C5 MAIN_PHONO_SEL 3 C5 1 D5 2 D5 MAIN_ANLG_EN REC_AD_MIC_SEL 7 C8 8 D4 14 C7 REC_DACOUT_SEL 10 C4 11 D3 12 D4 14 D7 MAIN_DACOUT_SEL 7 C8 REC_AD_PHO75_SEL ANLG_7_8_DIR_SEL 1 A5 2 A5 HEADP_ZONE_SEL 16 A8 HEADP_REC_SEL 16 A8 ANLG_4_5_DIR_SEL 1 A5 2 A5 NC S2 S1 MAIN_DAC_LATCH_0 10 C7 56 R200 ADA_SDATA_IN 15 C6 TUN_SCLK 15 A5 7 A2 REC_ADC_192K_EN REC_ADC_96K_EN 7 A2 7 A2 ...

Page 231: ... D5 6 D4 7 B7 8 B6 9 B6 10 C7 11 C7 12 C7 13 C7 14 B5 4 D5 8 C7 10 C7 11 C7 12 C7 13 C7 14 B5 15 A5 ADA_SDATA_OUT ADA_TUN_CE 15 A5 7 A2 15 C3 REC_ADC_FS 8 C7 15 C3 REC_DAC_FS 4 A4 5 A4 6 A4 10 C7 11 C7 12 C7 13 C7 15 C3 MAIN_FS 8 D7 15 B3 REC_DAC_FS64 7 A2 15 B3 REC_ADC_FS64 8 D7 15 C3 REC_DAC_I2S_OUT 4 A4 5 A4 6 A4 10 C7 11 D7 12 D7 13 D7 15 B3 MAIN_FS64 13 C7 15 C3 MAIN_I2S_OUT4 12 C7 15 C3 MAIN...

Page 232: ... 5 23 03 CBV 5 21 03 2 CHANGED PER DCR 030407 00 RWH MAG 11 21 02 11 20 02 CW CBV 11 20 02 1 CHANGED PER DCR 021107 00 RWH RWH CBV CW MAG 8 29 02 8 29 02 8 28 02 8 27 02 15 15 GND 060 15579 5 SCHEM ANALOG I O BD RV8 FROM POWER SUPPLY 12V FOR TUNER MODULE 5VA REGULATOR 5VR REGULATOR HEADPHONE OUTPUT LEFT RIGHT FRONT LEFT RIGHT REC LEFT RIGHT ZONE POWER SUPPLY HEADPHONE TEST POINTS 15V SOURCE 15V SO...

Page 233: ...5 MAG 10 7 03 10 7 03 CW CBV 10 6 03 CHANGED PER DCR 030729 00 RWH MAG 5 23 03 5 23 03 CW 5 23 03 CBV 5 21 03 2 CHANGED PER DCR 030407 00 RWH MAG 11 21 02 11 20 02 CW CBV 11 20 02 1 CHANGED PER DCR 021107 00 RWH RWH CBV CW MAG 8 29 02 8 29 02 8 28 02 8 27 02 060 15579 SCHEM ANALOG I O BD RV8 3 3V DIGITAL BYPASS CAPACITORS 5V DIGITAL BYPASS CAPACITORS 5V ANALOG BYPASS CAPACITORS 11 14 02 BYPASS CAP...

Page 234: ...REVISION MAG 8 28 02 8 28 02 CW ECM 8 28 02 RWH 8 9 02 SYNC STRIPPER ON SCREEN DISPLAY COMPONENT VIDEO VIDEO CONVERSION POWER INTERFACE CONNS CHANGED PER DCR 030106 00 1 COMPOSITE VIDEO OUTPUTS 1 23 03 MAG 1 23 03 CW ECM 1 21 03 S VIDEO INPUTS RWH 1 13 03 2 CHANGED PER DCR 030421 00 6 LAST REFERENCE DESIGNATORS USED C183 D11 E3 FB11 J20 L7 CPLD CONTROL REGISTERS PLL RWH 5 20 03 MAG 5 22 03 5 22 03...

Page 235: ...EO OUT OSD COMPOSITE VIDEO MAIN 060 15589 SCHEM VIDEO BD RV8 MAIN MAIN BYPASS CHANGED PER DCR 030106 00 3 ECM 10 9 03 MAG 10 16 03 CW 10 16 03 CHANGED PER DCR 030623 00 10 2 15589 3 2 10 16 2003_16 28 MORPHEN1 9 C3 7 1 4 5 8 3 6 2 U16 7 C2 OSD_Y C_OUT R126 R127 MSTHRU 9 B3 OSD_SY_OUT 7 C2 7 C2 OSD_C_OUT 5 B8 SC_MAIN1_D SY_MAIN1_D 5 C8 9 C3 MTHRU OSD_C_IN 5 C8 7 C8 R212 R211 R217 R215 5 C8 7 D8 OSD...

Page 236: ...23 03 MAG 1 23 03 CW RWH 1 13 03 ECM 1 21 03 CHANGED PER DCR 030106 00 1 MAG 8 28 02 8 28 02 CW ECM 8 28 02 RWH 8 9 02 ZONE2 S VIDEO OUT ZONE2 OUT COMPOSITE VIDEO SCHEM VIDEO BD RV8 060 15589 ZONE 2 3 10 16 2003_16 28 10 3 15589 3 3 9 C3 RECSVID_YOFF SYREC SYREC1 RECVID_SEL1 9 C3 4 1 3 2 8 U18 R4 R5 R167 R162 C79 R150 NC NC 8 2 3 1 4 U19 4 7 5 6 8 U19 CVID_REC2 1 A4 CVID_REC1 1 A4 R163 SC4 1 C7 2 ...

Page 237: ...CHANGED PER DCR 030421 00 RWH 5 20 03 1 23 03 MAG 1 23 03 CW RWH 1 13 03 ECM 1 21 03 CHANGED PER DCR 030106 00 1 MAG 8 28 02 8 28 02 CW ECM 8 28 02 RWH 8 9 02 OUT ZONE3 SCHEM VIDEO BD RV8 060 15589 COMPOSITE VIDEO ZONE 3 3 15589 3 4 4 10 10 16 2003_16 28 NC NC NC CVID3 1 A6 C47 R134 8 6 5 7 4 U5 10 A6 CVID_ZON2 SCZON2 SYZON2 NC 4 7 5 6 8 U6 8 2 3 1 4 U6 Z2SVID_SEL0 9 B3 Z2SVID_SEL2 9 B3 Z2SVID_SEL...

Page 238: ...030421 00 RWH 5 20 03 1 23 03 MAG 1 23 03 CW RWH 1 13 03 ECM 1 21 03 CHANGED PER DCR 030106 00 1 MAG 8 28 02 8 28 02 CW ECM 8 28 02 RWH 8 9 02 060 15589 SCHEM VIDEO BD RV8 VIDEO CONVERSION VIDEO DECODER VIDEO ENCODER 3 10 16 2003_16 28 10 5 5 15589 3 NC NC AOUT C151 9 B6 XCLK DEC_XRH 6 D7 9 B7 47 R224 R226 47 9 C6 PLAYSPEED XRV XCLK PD0 PD1 PD2 PD7 PD6 PD5 PD4 PD3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 P...

Page 239: ...02 PB PB PR PR PR Y Y INPUT 1 INPUT 3 INPUT 2 COMPONENT VIDEO INPUTS SCHEM VIDEO BD RV8 060 15589 COMPONENT VIDEO COMPONENT VIDEO OUTPUTS PR SPARES Y PB Y PB COMPONENT ENCODER FILTERS L sync 3 6 15589 3 10 10 16 2003_16 28 6 R103 9 B3 SYNC_EN R86 R87 Q20 R88 1 2 3 U2 6 D7 6 C2 6 C5 3 3VA_B R105 C34 R102 CNV_PB CNV_PB CNV_Y CNV_Y CNV_PR CNV_PR PY_IN_SEL 8 6 4 RY3 6 D7 6 C5 3 3VA_B 4 6 8 RY2 R90 R99...

Page 240: ...8 03 MAG 5 22 03 5 22 03 CW ECM 5 20 03 2 CHANGED PER DCR 030421 00 RWH 5 20 03 1 23 03 MAG 1 23 03 CW RWH 1 13 03 ECM 1 21 03 CHANGED PER DCR 030106 00 1 MAG 8 28 02 8 28 02 CW ECM 8 28 02 RWH 8 9 02 4XFSC OSCILLATORS FONT MEMORY 060 15589 SCHEM VIDEO BD RV8 ON SCREEN DISPLAY ON SCREEN DISPLAY 3 7 10 16 2003_16 28 10 7 15589 3 OSD_VSYNC H OSD_CSYNC NC C120 V 9 A3 VIDEO_DATA5 9 A3 OSD_CS5 OSD_SCLK...

Page 241: ...K LF353 3 3VD 5VV 74HC4053 Y X Z S INH VEE VSS VCC 220PF CHANGED PER DCR 030623 00 ECM 10 9 03 MAG 10 16 03 CW 10 16 03 3 RWH 10 8 03 5 20 03 ECM CW 5 22 03 5 22 03 MAG 2 CHANGED PER DCR 030421 00 5 20 03 RWH 1 23 03 MAG 1 23 03 CW RWH 1 13 03 ECM 1 21 03 CHANGED PER DCR 030106 00 1 MAG 8 28 02 8 28 02 CW ECM 8 28 02 RWH 8 9 02 SYNC STRIPPER SYNC STRIPPER SCHEM VIDEO BD RV8 060 15589 DC RESTORER 3...

Page 242: ...TDO TDI TMS RED BLK YEL VIO WHT GRN MAG 8 28 02 8 28 02 CW ECM 8 28 02 RWH 8 9 02 SCHEM VIDEO BD RV8 060 15589 JTAG PROGRAMMING PORT ENCODER CLOCK PLL FLASH INTERFACE CPLD CONTROL REGISTERS PLL 3 9 10 16 2003_16 28 15589 3 9 10 NC NC NC R81 5 C5 PLAYSPEED 6 D7 HVSYNC 5 B5 6 D7 DEC_VS JTAG_TDO JTAG_TMS JTAG_TDI 10 A5 VIDEO_RST DEC_HS 5 B5 ENC_15KHZ ENC_RES 5 B4 SYNC_EN 6 C7 NC 2 A8 MSVID_SEL0 13 11...

Page 243: ...ND CASE VIN CHANGED PER DCR 030623 00 ECM 10 9 03 MAG 10 16 03 CW 10 16 03 10 8 03 RWH MAG 5 22 03 5 22 03 ECM 5 20 03 5V 1 23 03 MAG 1 23 03 CW RWH 1 13 03 ECM 1 21 03 CHANGED PER DCR 030106 00 1 MAG 8 28 02 8 28 02 CW ECM 8 28 02 RWH 8 9 02 CONNECTOR POWER SUPPLY SCHEM VIDEO BD RV8 060 15589 POWER INTERFACE CONNS MAIN BOARD CONNECTOR BYPASS CAPACITORS 5V REGULATOR 3 3V 15V CW 3 3V REGULATOR 3 2 ...

Page 244: ...OAK PARK BEDFORD MA 01730 1UH 5VD 2003 Lexicon Inc GROUND POWER 4 GROUND GROUND CHASSIS ANALOG GROUND DIGITAL NOTES 1 UNLESS OTHERWISE INDICATED RESISTORS ARE 1 10W 2 UNLESS OTHERWISE INDICATED RESISTORS ARE 5 3 UNLESS OTHERWISE INDICATED CAPACITORS ARE UF V 1 0 5 LAST REFERENCE DESIGNATORS USED C5 D1 FB1 J1 L1 R1 U1 RWH 060 16139 SCHEM VCO BD MCLK 3 3 03 ECM CW KAB 3 5 03 3 7 03 3 11 03 3 18 2003...

Page 245: ...HECKED TITLE exicon REV 3 OAK PARK BEDFORD MA 01730 470PF 100 GROUND GROUND DIGITAL NOTES ANALOG GROUND CHASSIS GROUND POWER 2003 Lexicon Inc 0 SCHEM SPKR EMI FILTER BD RV8 060 16189 BINDING POST FILTER 1 2 LAST REFERENCE DESIGNATORS USED BP2 C2 3 COMPONENTS MARKED WITH ARE NOT INSTALLED RWH 5 1 03 5 1 03 ECM 5 8 03 CW MAG 5 8 03 C1 C2 1 5 12 2003_9 05 1 16189 0 1 BP1 BP2 470PF 100 ...

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Page 248: ...Harman Specialty Group 3 Oak Park Bedford MA 01730 1413 USA Customer Service Telephone 781 280 0300 Service Fax 781 280 0499 www lexicon com Part No 070 17537 Rev 0 ...

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