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DSP 1 and 2 Configuration (U16 and U34)

DSP 1 and DSP 2 are Analog Devices ADSP21161N 32-bit SHARC Microcomputers. They come
packaged in a 255 position Ball Grid Array. The IO pins on these devices are not 5 volt tolerant,
necessitating the level shifters on sheet 2 of this schematic set. These DSP devices are responsible for
proprietary signal processing, such as Bass Management, Room Equalization, and LOGIC7 Surround
Decoding. These blocks represent the sections of the Proprietary Algorithm DSPs that configure their
default operation.

Clock I/O and Configuration

Device Pins: CLKIN (P12), XTAL (R13), CLKOUT (R9), CLK_CFG[1:0] (N12:13), CLKDBL/ (R12)

The DSP devices each have a clock input of 12.500 MHz, as provided by buffer gates U46. The clock-
input pins

CLKIN

are impedance matched by R161 and R162. Since this topology uses an external

oscillator rather than a crystal, the

XTAL

pins on each device are left floating and unused. The core clock

frequency is derived from this input clock by internal PLL circuits. The PLLs are configured for X4
operation by the

CLK_CFG[1:0]

pins by hardwiring them to a binary value of 10, setting the core

frequency to 50MHz. This core frequency is then further multiplied by two, by hardwiring the

CLKDBL/

to a logic 0. This makes the final core frequency 100MHz. The

CLKOUT

pin on each device connects to a

test-point

ACKO

BCKO

depending upon which DSP device is of interest. The clock signals appearing

here are 2X the input clock, or 25.00 MHz.

Interrupt Requests

Device Pins: IRQ2/ (J1), IRQ1/ (H4), IRQ0/ (H2)

The ADSP21161N has provision for three interrupt sources. In this application, only one is used,

IRQ0/

with the unused IRQ lines pulled to an inactive high state.

IRQ0/

monitors an active low interrupt provided

by the FPGA, which is generated coincident with the rising edge of the word clock divided by eight (i.e.
14.112MHz / 8 = 1.764MHz). Therefore, for every eight audio samples an interrupt is generated to the
DSPs.

Bus Arbitration

Device Pins: RBPA (B3), HBR/ (R10), HBG/ (R11), CS/ (N11), PA (R6), BR6/:BR1/ (M7, N7, P7, R7, N8,
P8), SBTS/ (P6), ID2 (J3), ID1 (J2), ID0 (J4)

These DSP devices operate independent of each other, therefore the bus arbitration capabilities of these
devices go unused and are wired to their inactive states. Since these devices share no resources each
DSP has an ID code of 000, as hardwired to the ID[2:0] pins.

JTAG Interface

Device Pins: EMU/ (C2), TMS (C1), TCK (D2), TRST/ (B1), TDI (B2), TDO (D1)

The DSPs support JTAG debugger access to the internal registers. Development code may also be
loaded via the JTAG port using the Analog Devices ICE development toolkit. The principle departure from
standard JTAG is the presence of the EMU/ signal. This is a status line that is read by the ICE tools. The
JTAG signals break out to JTAG connector J17. Jumpers W7 through W10 implement device selection for
JTAG. By selective jumpering one may talk to U16, U34, or U34 in series with U16. The following
diagrams illustrate the various configurations. This function is used only in development and as such is
not used in the standard build of this product. Note that R159 and R160 must be removed before using
JTAG as they provide default termination of the TRST and TCK pins during normal operation.

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