THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
1_DDR
2014/02/04
12
NC5_S7LR(M1A)
A-MWEB
A-MA7
A-MDQL5
A-MBA2
A-MCASB
A-MA8
A-MA12
R1208
56
1%
DDR_EXT
A-MODT
A-MA2
A-MDQU7
A-MDQL0
A-MDQL2
C1201
0.1uF
DDR_EXT
A-MA14
C1202
1000pF
DDR_EXT
A-MDQSLB
A-MA4
R12011K
1%
DDR_EXT
A-MVREFDQ
A-MRESETB
A-MCKB
A-MDQL3
A-MDMU
A-MVREFCA
R1202
1K
1%
DDR_EXT
A-MDQL4
A-MBA1
R1205
1K
1%
DDR_EXT
A-MDQU2
R1203
240
1%
DDR_EXT
A-MDQSU
R1206
10K
DDR_EXT
A-MBA0
A-MA5
A-MDQU1
A-MDQSL
A-MA9
R1207
56
1%
DDR_EXT
C1214
1000pF
DDR_EXT
A-MCKE
A-MVREFDQ
A-MDML
A-MA10
A-MDQU0
A-MA13
A-MDQU3
A-MA11
A-MDQU6
A-MDQSUB
C1213
0.1uF
DDR_EXT
A-MRASB
A-MVREFCA
A-MDQU4
A-MDQU5
A-MDQL7
A-MA0
A-MDQL6
A-MA3
A-MDQL1
A-MA1
A-MA6
A-MCK
R1204
1K
1%
DDR_EXT
+1.5V_DDR
C1217
0.1uF
OPT
C1210
0.1uF
DDR_EXT
C1206
0.1uF
DDR_EXT
C1211
0.1uF
DDR_EXT
C1207
0.1uF
DDR_EXT
C1208
0.1uF
DDR_EXT
C1204
0.1uF
DDR_EXT
C1212
0.1uF
DDR_EXT
C1209
0.1uF
DDR_EXT
C1205
0.1uF
DDR_EXT
C1215
0.01uF
50V
DDR_EXT
C1218
0.1uF
OPT
C1224
0.1uF
OPT
H5TQ2G63DFR-PBC
IC1201-*2
DDR_1600_2G_HYNIX_OLD
EAN61829203
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
C1216
10uF
10V
OPT
C1203
10uF
10V
DDR_EXT
C1219
1uF
OPT
C1220
1uF
OPT
C1221
1uF
OPT
C1222
1uF
OPT
C1223
1uF
OPT
+1.5V_DDR
+1.5V_DDR
+1.5V_DDR
+1.5V_DDR
+1.5V_DDR
A-MA13
A-MA14
A-MA7
A-MA10
A-MA1
A-MA8
A-MA3
A-MA0
A-MA4
A-MA6
A-MA11
A-MA9
A-MA5
A-MA2
A-MA12
A-MBA0
A-MBA1
A-MBA2
A-MCKE
A-MCK
A-MCKB
A-MCASB
A-MWEB
A-MRASB
A-MODT
A-MRESETB
A-MDMU
A-MDML
A-MDQSU
A-MDQSUB
A-MDQSL
A-MDQSLB
A-MDQL4
A-MDQL0
A-MDQL3
A-MDQL7
A-MDQL5
A-MDQL2
A-MDQL6
A-MDQL1
A-MDQU1
A-MDQU3
A-MDQU0
A-MDQU4
A-MDQU5
A-MDQU2
A-MDQU6
A-MDQU7
R1209
240
1%
A/B_DDR3_CS
A/B_DDR3_CS
H5TQ1G63EFR-PBC
IC1201
DDR_1600_1G_HYNIX
EAN61829003
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
NC_7
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
IC101
LGE2132(M1A_256M)
M1A_256M_UO3
B_DDR3_A[0]
E11
B_DDR3_A[1]
F12
B_DDR3_A[2]
D10
B_DDR3_A[3]
B10
B_DDR3_A[4]
E15
B_DDR3_A[5]
B11
B_DDR3_A[6]
F14
B_DDR3_A[7]
C11
B_DDR3_A[8]
D14
B_DDR3_A[9]
A12
B_DDR3_A[10]
F16
B_DDR3_A[11]
D13
B_DDR3_A[12]
D15
B_DDR3_A[13]
C12
B_DDR3_A[14]
E13
B_DDR3_BA[0]
A9
B_DDR3_BA[1]
D16
B_DDR3_BA[2]
A10
B_DDR3_MCLK
C13
B_DDR3_MCLKZ
B13
B_DDR3_MCLKE
E17
B_DDR3_ODT
B8
B_DDR3_RASZ
C8
B_DDR3_CASZ
B9
B_DDR3_WEZ
D11
B_RESET
F10
B_DDR3_CS0
D12
B_DDR3_DQSL
A19
B_DDR3_DQSU
B18
B_DDR3_DQML
C16
B_DDR3_DQMU
D21
B_DDR3_DQSBL
C18
B_DDR3_DQSBU
C17
B_DDR3_DQL[0]
A20
B_DDR3_DQL[1]
A16
B_DDR3_DQL[2]
C19
B_DDR3_DQL[3]
C15
B_DDR3_DQL[4]
C20
B_DDR3_DQL[5]
C14
B_DDR3_DQL[6]
B21
B_DDR3_DQL[7]
B15
B_DDR3_DQU[0]
F18
B_DDR3_DQU[1]
D19
B_DDR3_DQU[2]
D17
B_DDR3_DQU[3]
E21
B_DDR3_DQU[4]
E19
B_DDR3_DQU[5]
D20
B_DDR3_DQU[6]
D18
B_DDR3_DQU[7]
F20
ZQ
E9
H5TQ2G63FFR-PBC
IC1201-*3
DDR_1600_2G_HYNIX_NEW
EAN61829204
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
K4B1G1646G-BCK0
IC1201-*1
DDR_1600_1G_SS
EAN61836301
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
K4B2G1646Q-BCK0
IC1201-*4
DDR_1600_2G_SS
EAN61848803
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
IC101-*1
LGE2131(M1A_128M)
M1A_128M_UO3
B_DDR3_A[0]
E11
B_DDR3_A[1]
F12
B_DDR3_A[2]
D10
B_DDR3_A[3]
B10
B_DDR3_A[4]
E15
B_DDR3_A[5]
B11
B_DDR3_A[6]
F14
B_DDR3_A[7]
C11
B_DDR3_A[8]
D14
B_DDR3_A[9]
A12
B_DDR3_A[10]
F16
B_DDR3_A[11]
D13
B_DDR3_A[12]
D15
B_DDR3_A[13]
C12
B_DDR3_A[14]
E13
B_DDR3_BA[0]
A9
B_DDR3_BA[1]
D16
B_DDR3_BA[2]
A10
B_DDR3_MCLK
C13
B_DDR3_MCLKZ
B13
B_DDR3_MCLKE
E17
B_DDR3_ODT
B8
B_DDR3_RASZ
C8
B_DDR3_CASZ
B9
B_DDR3_WEZ
D11
B_RESET
F10
B_DDR3_CS0
D12
B_DDR3_DQSL
A19
B_DDR3_DQSU
B18
B_DDR3_DQML
C16
B_DDR3_DQMU
D21
B_DDR3_DQSBL
C18
B_DDR3_DQSBU
C17
B_DDR3_DQL[0]
A20
B_DDR3_DQL[1]
A16
B_DDR3_DQL[2]
C19
B_DDR3_DQL[3]
C15
B_DDR3_DQL[4]
C20
B_DDR3_DQL[5]
C14
B_DDR3_DQL[6]
B21
B_DDR3_DQL[7]
B15
B_DDR3_DQU[0]
F18
B_DDR3_DQU[1]
D19
B_DDR3_DQU[2]
D17
B_DDR3_DQU[3]
E21
B_DDR3_DQU[4]
E19
B_DDR3_DQU[5]
D20
B_DDR3_DQU[6]
D18
B_DDR3_DQU[7]
F20
ZQ
E9
IC101-*2
LGE2134(256M)
M1A_256M_UO4
B_DDR3_A[0]
E11
B_DDR3_A[1]
F12
B_DDR3_A[2]
D10
B_DDR3_A[3]
B10
B_DDR3_A[4]
E15
B_DDR3_A[5]
B11
B_DDR3_A[6]
F14
B_DDR3_A[7]
C11
B_DDR3_A[8]
D14
B_DDR3_A[9]
A12
B_DDR3_A[10]
F16
B_DDR3_A[11]
D13
B_DDR3_A[12]
D15
B_DDR3_A[13]
C12
B_DDR3_A[14]
E13
B_DDR3_BA[0]
A9
B_DDR3_BA[1]
D16
B_DDR3_BA[2]
A10
B_DDR3_MCLK
C13
B_DDR3_MCLKZ
B13
B_DDR3_MCLKE
E17
B_DDR3_ODT
B8
B_DDR3_RASZ
C8
B_DDR3_CASZ
B9
B_DDR3_WEZ
D11
B_RESET
F10
B_DDR3_CS0
D12
B_DDR3_DQSL
A19
B_DDR3_DQSU
B18
B_DDR3_DQML
C16
B_DDR3_DQMU
D21
B_DDR3_DQSBL
C18
B_DDR3_DQSBU
C17
B_DDR3_DQL[0]
A20
B_DDR3_DQL[1]
A16
B_DDR3_DQL[2]
C19
B_DDR3_DQL[3]
C15
B_DDR3_DQL[4]
C20
B_DDR3_DQL[5]
C14
B_DDR3_DQL[6]
B21
B_DDR3_DQL[7]
B15
B_DDR3_DQU[0]
F18
B_DDR3_DQU[1]
D19
B_DDR3_DQU[2]
D17
B_DDR3_DQU[3]
E21
B_DDR3_DQU[4]
E19
B_DDR3_DQU[5]
D20
B_DDR3_DQU[6]
D18
B_DDR3_DQU[7]
F20
ZQ
E9
IC101-*3
LGE2133(128M)
M1A_128M_UO4
B_DDR3_A[0]
E11
B_DDR3_A[1]
F12
B_DDR3_A[2]
D10
B_DDR3_A[3]
B10
B_DDR3_A[4]
E15
B_DDR3_A[5]
B11
B_DDR3_A[6]
F14
B_DDR3_A[7]
C11
B_DDR3_A[8]
D14
B_DDR3_A[9]
A12
B_DDR3_A[10]
F16
B_DDR3_A[11]
D13
B_DDR3_A[12]
D15
B_DDR3_A[13]
C12
B_DDR3_A[14]
E13
B_DDR3_BA[0]
A9
B_DDR3_BA[1]
D16
B_DDR3_BA[2]
A10
B_DDR3_MCLK
C13
B_DDR3_MCLKZ
B13
B_DDR3_MCLKE
E17
B_DDR3_ODT
B8
B_DDR3_RASZ
C8
B_DDR3_CASZ
B9
B_DDR3_WEZ
D11
B_RESET
F10
B_DDR3_CS0
D12
B_DDR3_DQSL
A19
B_DDR3_DQSU
B18
B_DDR3_DQML
C16
B_DDR3_DQMU
D21
B_DDR3_DQSBL
C18
B_DDR3_DQSBU
C17
B_DDR3_DQL[0]
A20
B_DDR3_DQL[1]
A16
B_DDR3_DQL[2]
C19
B_DDR3_DQL[3]
C15
B_DDR3_DQL[4]
C20
B_DDR3_DQL[5]
C14
B_DDR3_DQL[6]
B21
B_DDR3_DQL[7]
B15
B_DDR3_DQU[0]
F18
B_DDR3_DQU[1]
D19
B_DDR3_DQU[2]
D17
B_DDR3_DQU[3]
E21
B_DDR3_DQU[4]
E19
B_DDR3_DQU[5]
D20
B_DDR3_DQU[6]
D18
B_DDR3_DQU[7]
F20
ZQ
E9
CLose to Saturn7M IC
CLose to DDR3
Option : Ripple Check !!!
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 47LB5610
Page 37: ......
