3-14
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
• PIN CONFIGURATION
I
O
_VDD
PLL_DVDD
IO_
V
SS
IO
_V
SS
P
L
L_AVD
D
IO_
V
SS
P
L
L
_
AVSS
P
L
L_DVSS
MLRC
K
MBCK
MSDIN0
MIC_LRCK
MIC_BCK
MIC_MCLK
PWM_HP_R_P
IO
_VSS
PWM2
_
P
PWM2
_
M
PWM3
_
P
PWM3
_
M
PWM4
_
P
PWM4
_
M
SPI/I2C
/CS/I2C_AD2
SI/I2C_AD0
SO/SDA
SCK/SCL
/RESET
SCAN_ENA
XIN
DVSS
IO_VSS
IO_
VSS
IO
_VSS
DVDD
DVSS
IO_VDD
IO
_VSS
MSDIN1
MSDIN2
SLRC
K
SBC
K
DVS
S
PWM5
_
P
PWM5
_
M
DVD
D
TEST_MODE3
DVSS
IO
_VSS
PWM6
_
P
PWM6
_
M
IO
_VSS
IO_
V
SS
PWM1_P
PWM1_M
OVERLOAD
IO_VSS
IO_VSS
SS
DIN1
EXT_MUTE
DVDD
IO_VDD
DVDD
SS
DIN0
MSDIN3
SS
DIN2
SSDIN3
IO_VSS
IO_VDD
MIC_SDIN
PWM_SWL_P
PWM_SWL_M
PWM_HP_L_P
PWM_HP_L_M
PWM_HP_R_M
IO
_VSS
PWM7
_
P
PWM7
_
M
PWM8
_
P
PWM8
_
M
EPD_ENA
TEST_MODE2
TEST_MODE1
IO_VSS
DMIX_LRCK
DMIX_BCK
DMIX_SDOUT
DMIX_MCLK
98
99
100
96
97
93
94
95
91
92
85
86
87
88
89
90
83
84
81
82
71
72
73
74
75
61
62
63
64
65
66
67
68
69
70
53
54
55
56
57
58
59
51
52
60
46
47
48
49
50
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
30
31
32
33
34
35
36
37
26
27
28
29
76
77
78
79
80
17
18
19
20
38
39
40
41
42
43
44
45
21
22
23
24
25
IO_VDD
IO_VSS
IO_VDD
DVDD
DVSS
IO_VDD
IO_VDD
IO_VDD
DVSS
DVDD
IO_VDD
PULSUS
PS9830B
XOUT