DESCRIPTION OF BLOCK DIAGRAM
- 10 -
1. Video Controller Part.
This part amplifies the level of video signal for the digital conversion and converts from the analog video signal to the
digital video signal using a pixel clock.
The pixel clock for each mode is generated by the PLL.
The range of the pixel clock is from 25MHz to 135MHz.
This part consists of the Scaler, ADC convertor and LVDS transmitter.
The Scaler gets the video signal converted analog to digital, interpolates input to 1280 X 1024 resolution signal and
outputs 8-bit R, G, B signal to transmitter.
