3. TECHNICAL BRIEF
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3. TECHNICAL BRIEF
3.2.2 Memory(N25Q128[VDFPN8 (F8)], U601)
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128 Mbit (16Mb 8)
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The N25Q128 is a 128 Mbit (16Mb x 8) serial Flash memory, with advanced write protection mechanisms.
It is accessed by a high speed SPI-compatible bus and features the possibility to work in XIP (“eXecution in
Place”) mode.
The N25Q128 supports innovative, high-performance quad/dual I/O instructions, these new instructions allow
to double or quadruple the transfer bandwidth for read and program operations.
Furthermore the memory can be operated with 3 different protocols:
Standard SPI (Extended SPI protocol)
Dual I/O SPI
Quad I/O SPI
The Standard SPI protocol is enriched by the new quad and dual instructions (Extended SPI protocol).
For Dual I/O SPI (DIO-SPI) all the instructions codes, the addresses and the data are always transmitted across
two data lines. For Quad I/O SPI (QIO-SPI) the instructions codes, the addresses and the data are always
transmitted across four data lines thus enabling a tremendous improvement in both random access time and
data throughput.
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The memory can work in “XIP mode”, that means the device only requires the addresses and not the
instructions to output the data. This mode dramatically reduces random access time thus enabling many
applications requiring fast code execution without shadowing the memory content on a RAM.
Figure 3.9 Memory
