39
Symbol Type
Description
A0-A10 Input
Address Inputs: A0-A10 are sampled during the BankActivate command (row address
A0-A10) and Read/Write command (column address A0-A7 with A10 defining Auto
Precharge) to select one location out of the 256K available in the respective bank. During
a Precharge command, A10 is sampled to determine if both banks are to be precharged
(A10 = HIGH). The address inputs also provide the op-code during a Mode Register Set
command.
CS# Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for
external bank selection on systems with multiple banks. It is considered part of the
command code.
RAS# Input
Row Address Strobe: The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS#
and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate
command or the Precharge command is selected by the WE# signal. When the WE# is
asserted "HIGH," the BankActivate command is selected and the bank designated by BS
is turned on to the active state. When the WE# is asserted "LOW," the Precharge
command is selected and the bank designated by BS is switched to the idle state after the
precharge operation.
CAS# Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK.
When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by
asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE#
"LOW" or "HIGH."
WE# Input
Write Enable: The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is
used to select the BankActivate or Precharge command and Read or Write command.
LDQM, UDQM
Input
Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent I/O buffer
controls. The I/O buffers are placed in a high-z state when LDQM/UDQM is sampled
HIGH. Input data is masked when LDQM/UDQM is sampled HIGH during a write cycle.
Output data is masked (two-clock latency) when LDQM/UDQM is sampled HIGH during a
read cycle. UDQM masks DQ15- DQ8, and LDQM masks DQ7-DQ0.
DQ0-DQ15 Input/Output
Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of
CLK. The I/Os are byte-maskable during Reads and Writes.
NC
-
No Connect: These pins should be left unconnected.
V
DDQ
Supply
DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V + 0.3V )
V
SSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity. ( 0 V )
V
DD
Supply
Power Supply: +3.3V +0.3V
V
SS
Supply
Ground
