46
68 WBLSH
3.3V
LVTTL
output,
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
Sample pulse for wobble signal.
69 ATFG
3.3V
LV TTL
Input,
SMT
Digital wobble signal (22.05
±
1 K Hz) input
70 WBLCLK
3.3V
LVTTL
output,
Slew rate,
4mA driving
Wobble processing clock (432.18K Hz) output for MT1516.
71 RFPDSH
3.3V
LVTTL
output,
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
Sample pulse control signal for RF read APC.
72 WFPDSH
3.3V
LV TTL
output,
Slew rate,
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
Sample pulse control signal for RF write APC.
206 WRSTOP
3.3V
LV TTL
Input,
SMT, 75K pull-down
Write procedure stop control input.
Miscellaneous Interface (4)
169 TEST_MODE
3.3V
LV TTL
input,
75K pull-down
Test mode, active high
170 PRST
3.3V
LV TTL
Input,
SMT
Power on reset input, high active.
74 XTALO Output
X`tal
output.
75 XTALI Input
X`tal
input. The working frequency is 33.8688 MHz.
Host Interface (31)
122 HRST#
3.3V
LV TTL
Input,
SMT, 75K pull-up
Host reset input. The active-low input is referred to as hardware
reset and is used to reset this chip.
142,140,138,
135,132,130,
127,124,123,
125,128,131,
133,136,139,
141
HD15 ~ HD0
3.3V LVTTL I/O,
Slew rate, SMT,
4mA, 6mA, 8mA,
12mA PDR,
40K(15K) PPU, 40K
(15K)PPD
Host Data bus. This is the 8-bit or 16-bit bi-directional data bus
to the host. The lower 8 bits, HD0–HD7, are used for 8-bit data
transfers. Normally, data transfers are 16-bit wide.
Note :
All pins except HD7 (no any pull) may be selectively
pull-up or pull-down with 40K resistant.(HD6~HD0 is 15K)
144 DMARQ
3.3V
LV TTL
output,
12mA driving
DMA request. This signal is used for DMA data transfers
between host and device and it shall be asserted by the MT1518
when it is ready to transfer data to or from the host. The
direction of data transfer is controlled by DIOR# and DIOW#.
145 DIOW#
3.3V
LV TTL
Input,
SMT, 40K pull-up
Device I/O write. Stop ultra DMA burst.
For Device I/O Write, this signal is the strobe signal asserted by
the host to write device register or the data port.
For Stop Ultra DMA, this signal shall be negated by the host
before data is transferred in an Ultra DMA burst and is asserted
by host during an Ultra DMA burst to signal the termination of
Ultra DMA burst.