3-31
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
BLOCK DIAGRAMS
1. OVERALL BLOCK DIAGRAM
SI
O
_S
P
I_
C
S
0
SI
O
_S
P
I_
MO
SI
SI
O
_S
P
I_
CL
K
IC1201
MX2
9LV
64
0M
TTC-90
FLASH
MEMORY
IC1202
HY
B2
5D51
2
160
C
E-5
DDR
SDRAM
E5_S
DRA
M
_D
QS[
1:0]
E5_SDRA
M
_D
QM[
1:0]
E5_SDRAM_C
L
K
1
E5_SDRA
M_C
L
K
#1
E5_SDRA
M_
D
Q
[15:0
]
E5_SDRAM_
A[
13:0
]
E5_SDRA
M_W
E#
E5_SDRA
M_CA
S
#
E5_SDRA
M_RA
S
#
E5_SDRAM_C
L
K
E
E5_SDRA
M_BA[
1:0]
ATA
P
I1_
D[
15:0]
AT
AP
I1
_ADD
[4
:0
]
/RS
T_ATAP
I1
ATA
P
I1_
DM
AR
Q
ATA
P
I1
_DI
O
W_
L
ATA
P
I1
_DI
O
R
_L
ATA
P
I1
_I
OR
DY
ATA
P
I1_
DM
A
A
C
K
_L
ATA
P
I1
_I
NT
RQ
ATA
P
I2_
D[
15:0]
AT
AP
I2
_ADD
[4
:0
]
/RS
T_ATAP
I2
ATA
P
I2_
DM
AR
Q
ATA
P
I2
_DI
O
W_
L
ATA
P
I2
_DI
O
R
_L
ATA
P
I2
_I
OR
DY
ATA
P
I2_
DM
A
A
C
K
_L
ATA
P
I2
_I
NT
RQ
HD
[15:0]
HD
[15:0]
E5_A
L
E
IC
1301
74LVT16373
Ad
d
ress
LA
T
C
H
HA
[21:6]
HA
[5:1][
23
:22
]
/E5_OE
/E5_
CS0
HD
[15:0]
/RS
T_HO
ST
IC1401
TSB
4
1
A
B
1
/RS
T_PH
Y
PHY
_L
INKON
PHY
_L
P
S
PHY
_L
RE
Q
PHY
_C
L
K
PHY
_CT
L
[1:0
]
PHY_
D
A
T
A[7:0]
DV
JA
C
K
TPA+
TPA-
TPB
+
TPB
-
SI
O
_S
P
I_
MI
SO
SPI_
CL
K
SPI_
CS
SPI_
MO
SI
SPI_
MIS
O
IC701
NE
C
MI
C
O
M
LOADER
INTERFACE
PML0
7
HDD
INTERFACE
PML0
8
IC
701 M
IC
O
M
/E5_L
WEn
IC1101
DM
N
8653
LSI
IC1101
DMN8
65
3
LSI
I/
O B
O
ARD
Timer B
O
ARD
VREF
/RST_SA
A7138
PMX
0
3
PC
DE
BU
G
G
IN
G
UA
R
T
UART2_CTS
UART2_RTS
UART2_TX
UART2_RX
HA
[5:1][
23
:22
]
/E5_OE
/E5_
CS0
/E5_L
WEn
HD
[15:
0]
E5_A
L
E
/RS
T_E5
/FL
A
S
H
/E5_
CS3
IC1204
G2995
IC901
SA
A
7138
AV
D
E
COD
E
R
Re
gist
er
AOU
T
_M
CL
KOU
T
VO
_D
[15:0]
SCL
SDA
AOU
T
_I
E
C9
58
VI
DEO
_I
N
T
VOU
T
_CL
K
HDMI
INTERFACE
HDMI
INTERFACE
PMH10
CEC
IC1501
TPS205
2
US
B_P
W
R
_EN
US
B_
OC
S
US
B_
D-
US
B_
D+
5V
D
US
B_
VC
C
USB
JA
C
K
Timer B
O
ARD
I/
O B
O
ARD
IC701
NE
C
MI
C
O
M
PMV
PM
V 01
1
VFD
Dis
p
la
y
Timer B
O
ARD
FL
D
_C
L
K/ENA/D
A
TA
F_C
V
BS
/A
L
/AR
RMC/KEY0/KEY
1
5.3VA/SW
5.3VA
-29A/
FD+/FD-
/RS
T
_TDA9984
PMV0
PM
V0