3. TECHNICAL BRIEF
- 56 -
•
Autonomous power down scenarios of Bluetooth and cellular system supported
•
Packages:
- P-VQFN-48 package
- P-WFLGA-56 package
•
Temperature range from -40
°
C up to 85
°
C
•
Boundary scan for interface lines via JTAG
3.17.2 Micro-Controller-Section
•
ARM7TDMI-STM ARM® Processor for protocol and application software
•
Wa Interrupt Module
3.17.3 Micro-Controller Memory
•
32 KByte RAM
•
256 KByte read only Program Memory
•
8 KByte Patch RAM
3.17.4 Interfaces
•
UART (Bluetooth - Interface, support for HCI UART and Three-Wire UART transport layers
with/without hardware handshaking) up to 3.25MBaud
•
Two channel PCM Audio interface with I2S mode
•
I2C Interface
•
Three channel full duplex CVSD trans coder
•
General Purpose I/Os
- External interrupt
- Port output levels available during low-power mode (VDD supplied)
•
Separate voltage domains for GPIO, UART and PCM interfaces
•
Control signal for requesting external (cellular) system clock
•
Multi frequency (e.g. 32.768 kHz) low power clock input
3.17.5. RF-Section
•
Integrated antenna switch to minimize external components count
•
Programmable RF transmit power between -55dBm...+6dBm
- Fine tuning in 2dB programmable steps also supported
•
20dBm power class 1 supported with external power amplifier
- Separate TX output interface to PA (bypass of internal T/R switch)
- Digital power step control
•
Receiver sensitivity typ. -90dBm
•
High performance integrated LNA with excellent blocking and inter modulation performance
•
Low-IF receiver topology eliminates external IF filters
•
Digital demodulation for optimum sensitivity and co- / adjacent channel performance
- Digital offset compensation, symbol and frame synchronization
•
RSSI information for power control
Summary of Contents for KE820
Page 1: ...Service Manual Model KE820 Service Manual KE820 Date August 2006 Issue 1 0 ...
Page 3: ... 4 ...
Page 5: ... 6 ...
Page 46: ...3 TECHNICAL BRIEF 47 Figure 18 EN SET port control method ...
Page 69: ...4 PCB layout 70 Figure 45 Main PCB bottom Figure 46 Main PCB bottom placement ...
Page 70: ...4 PCB layout 71 Figure 47 Sub PCB top Figure 48 Sub PCB top placement ...
Page 71: ...4 PCB layout 72 Figure 49 Sub PCB bottom Figure 50 Sub PCB bottom placement ...
Page 114: ...6 Download S W upgrade 115 6 2 Download program user guide ...
Page 115: ... 116 6 Download S W upgrade ...
Page 116: ... 117 6 Download S W upgrade ...
Page 117: ... 118 6 Download S W upgrade ...
Page 124: ... 125 8 PCB LAYOUT ...
Page 125: ... 126 8 PCB LAYOUT ...
Page 126: ... 127 8 PCB LAYOUT ...
Page 127: ... 128 8 PCB LAYOUT ...
Page 141: ... 142 ...
Page 161: ...Note ...
Page 162: ...Note ...