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Copyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3. TECHNICAL BRIEF
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3.4.1 32.768KHz Time Base
The 32768 Hz clock is always running. It’s mainly used as the time base of the Real Time Clock(RTC)
module, which maintains time and date with counters. Therefore, both the 32768Hz oscillator and the RTC
module is powered by separate voltage supplies that shall not be powered down when the other supplies
do.
In low power mode, the 13Mhz time base is turned off, so the 32768Hz clock shall be employed to update
the critical TDMA timer and Watchdog Timer. This time base is also used to clocks the keypad scanner
logic
3.4.2 26MHz Time Base
Since PLL are based on 13MHz reference clock. There is an ½-dividers for PLL existing to allow using
26MHz DCXO.
There are 2 phase-locked loops(PLL) in MT6253. The UPLL generates 624Mhz clock output, then a
frequency divider further divide 6, and 13 to generate fixed 103Mhz, and 48Mhz for GSM_CLOCK and
USB_CLOCK and DSP_CLOCK. These four primary clocks then feed into GSM, USB, MCU and DSP Clock
Domain, respectively.
These 2 PLLs require no off-chip components for operations and can be turn off in order to save power.
After power-on, the PLLs are off by default and the source clock signal is selected through multiplexers.
The software shall take cares of the PLL lock time while changing the clock selections. The PLL and usages
are listed below.
- PLL supply four clock source : MCU_CLOCK(104~113Mhz), DSP_CLOCK(104~113Mhz),
GSM_CLOCK(104Mhz) and USB_CLOCK(48Mhz)
- For DSP/MCU system clock, MCU_CLOCK and DSP_CLOCK. The outputted 104~113Mhz clock is
controlled by MCU for 500Khz per step and settled time is under 100uS. The clock is also connected to
DSP/MCU DCM (dynamic clock manager) for dynamically adjusting clock rate by digital clock divider.
MCU_CLOCK paces the operations of the MCU cores, MCU memory system, and MCU peripherals as well
- Modem system clock, GSM_CLOCK, which paces the operations of the GSM/GPRS hardware,
coprocessors as well. The outputted 104Mhz clock is connecter to GSM_DCM for dynamically adjusting
clock rate by digital clock divider. Typically the GSM_DCM output clock no more than 52Mhz.
Note that PLL need some time to become stable after being powered up. The software shall take cares of
the PLL lock time before switching them to the proper frequency. Usually, a software loop longer than the
PLL lock time is employed to deal with the problem.
For power management, the MCU software program may stop MCU Clock by setting the Sleep Control
Register. Any interrupt requests to MCU can pause the sleep mode, and thus MCU return to the running
mode.
AHB also can be stop by setting the Sleep Control Register. However the behavior of AHB in sleep mode is
a little different from that of MCU. After entering Sleep Mode, it can be temporarily waken up by any
“hreq”(bus request), and then goes back to sloop automatically after all “hreqs” de-assert. Any
transactions can take place as usual in sleep mode, and it can save power while there is no transaction on
it. However the penalty is losing a little system efficiency for switching on and off bus clock, but the
impact is small
3. TECHNICAL BRIEF
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