4-8
Register Descriptions
MAP_OFF
QAM Mapping Off
R/W 2
When this bit is 1, the L64777 stops QAM mapping.
When this bit is 0, the L64777 uses DVB-compliant
mapping. The reset value is 0.
AMPL
PLL Oscillator Amplitude
R/W 1
This controls the amplitude of the on-chip PLL oscillator.
When this bit is 0, the L64777 is in low-power mode with
higher jitter. When this bit is 1, the L64777 is in
high-power mode with lower jitter. For normal operation,
set this bit to 0.
RES
Reserved
0
This bit is reserved.
4.1.8 Registers 7 and 8
RES
Reserved
15
This bit is reserved.
ICNT_O
Initial OCLK Value
R/W [14:0]
This is a 15-bit initial value for the OCLK PLL feedback
division. The reset value for bit 3 is 1; for all other bits it
is 0.
4.1.9 Registers 9 and 10
RES
Reserved
15
This bit is reserved.
ICNT_I
Initial ICLK Value
R/W [14:0]
This is a 15-bit initial value for the ICLK PLL reference
division. The reset value for bit 1 is 1; for all other bits it
is 0.
15
14
0
RES
ICNT_O
15
14
0
RES
ICNT_I
Summary of Contents for L64777
Page 1: ...L64777 DVB QAM Modulator Order Number I14031 A Technical Manual June 2000...
Page 10: ...x Contents...
Page 14: ...1 4 Introduction...
Page 90: ...5 10 Signals...
Page 110: ...A 8 Programming the L64777 in Serial Host Interface Mode...
Page 116: ...C 2 Monitoring Device Internal Signals...
Page 124: ......
