255-700-019
3-21
PacketStar
™
PSAX 20 Access Concentrator User Guide
, Issue 1
Release 6.3.0
Chapter 3 System Features
PSAX 20 Software Features
The firmware download is performed under the control of two Interworking
Functions (IWFs) resident in the Access Concentrator CPU, and in the I/O or
server module, respectively. Once the binaries are downloaded, the modules
execute the downloaded code that controls the module.
A user does not need to take the initiative to download an I/O or server
module’s firmware separately from the Access Concentrator CPU software
upgrade. When the Access Concentrator software is upgraded using the SRD
Download Configuration window (see Chapter 7, "Upgrading and Backing
Up the AC System Software"), the system reboots and all firmware of the I/O
and server modules (in the rebooted chassis) is also upgraded.
You can use the following procedure to revert to an older firmware release if
a module is not working properly with its current firmware.
Access Concentrator I/O modules released with Access Concentrator 6.0.0
software release are supported by the Firmware Release Control feature. The
I/O modules that were released before the Access Concentrator 6.0.0
software release will work in the Access Concentrator chassis, but are not
supported by the Firmware Release Control feature.
Forward Error Correction
The forward error correction (FEC) feature is a combination of functions
designed to protect data transmission in a noisy communications
environment, such as traffic transmitted across satellite and line-of-sight
radio-frequency circuits. Most of these types of circuits transmit at the rate of
2.048 Mbps or slower. The three stages of FEC are multiple redundancy
addressing, cell encoding, and cell scrambling. Since these FEC functions are
applied in conjunction with LANET, which helps maintain cell-delineation
capability up to random 10
-2
bit error rate (BER) with 0.625 percent
bandwidth overhead, maximum protection is obtained.
Multiple redundancy addressing sets up multiple virtual circuits to the same
destination. The addresses for the circuits are within the error space of the
principal one used for actual transmission. Thus, the most probable error
patterns occurring in the address field cause the address to be changed to
another valid one. To tolerate 2-bit random errors or 5-bit burst errors, 526
addresses are required for each channel. This is not a serious constraint
because high-noise, low-speed links are normally used by only a small
number of users. The more constraining situation, however, is that the
signaling channel VPI value 0 and VCI value 5 is within 2 bit-errors of the
null cell address (0,0). Thus, in high-error conditions, signaling is inhibited.
The PTI and GFC fields need to be separately protected with the payload. The
user needs only to set up a single connection using a VPI value 0 and a VCI
value in the range from 32 to 92. This provides for 60 simultaneous, noise-
tolerant base connections. Each connection (ATM-to-ATM, VCC, PVC) is
created between an ATM-enabled port on a Multi-Serial module and another
ATM port (such as the OC-3c and the STM-1 modules). Internally within the
Access Concentrator chassis, the connection is routed through the CPU
module for the cell-encoding stage.
Summary of Contents for PacketStar PSAX 20
Page 399: ......
