10-4
4. Digital Signal Process Block Diagram
FL11.10BLD
DIGIT
AL MAIN CB
A UNIT
IC3005
(DIGIT
AL SIGNAL PR
OCESS)
CN3005
LL
V1(+)
21
LL
V1(-)
20
LL
V0(+)
23
LL
V0(-)
22
LL
V2(+)
19
LL
V2(-)
18
LL
V3(+)
13
LL
V3(-)
12
LL
V4(+)
11
LL
V4(-)
10
LL
V5(+)
9
LL
V5(-)
8
LL
VCLK(+)
16
LL
VCLK(-)
15
TP
6
POL
5
CPV
4
OE1
3
STV
1
LV
D
S
TX
DIGIT
AL
SIGNAL
PR
OCESS
A/D
CONVER
TER
S-VIDEO-Y
-IN
SW
B12
D8
A11
S-VIDEO-C-IN
A8
VIDEO-IN
B7
COM-VIDEO-Pr-IN
COM-VIDEO-Pb-IN
COM-VIDEO-Y
-IN
A7
B8
C12
D
VD-Pr
D
VD-Pb
DV
D
-Y
A12
IF-A
GC
HDMI-IN1
HDMI-IN2
JK3003
TMDS-D0(+)
TMDS-D0(-)
TMDS-D1(+)
TMDS-D1(-)
TMDS-D2(+)
TMDS-D2(-)
SD
A
SCL
7
9
4
6
1
3
10
12
16
15
7
9
4
6
1
3
10
12
16
15
JK3004
TMDS-D0(+)
TMDS-D0(-)
TMDS-D1(+)
TMDS-D1(-)
TMDS-D2(+)
TMDS-D2(-)
TMDS-CLOCK(+)
TMDS-CLOCK(-)
SD
A
SCL
TMDS-CLOCK(+)
TMDS-CLOCK(-)
DEMODULA
T
OR
/MPEG DECODER
A
UDIO I/F
T
O A
UDIO
BLOCK DIA
GRAM
AMP(L)-OUT
AMP(R)-OUT
C7-SPDIF
G1
G2
L2
B1,B9,C2,C8,
D1,D3,D7,D9,
F1,F9,G2,G8,
H1,H3,H7,H9
M2,M3,M7,M8,
N2,N3,N7,N8,
P2,P3,P7,P8,R2
(DDR2 SDRAM)
HDMI
I/F
AU
D
IO
DECODER
DIF-OUT1
DIF-OUT2
IF-A
GC
T
O VIDEO
BLOCK DIA
GRAM
VIDEO
DECODER
S-VIDEO-SW
S-VIDEO-SW
B5
A
UDIO(R)
C4
A
UDIO(L)
A2
D
VD-A
UDIO(R)
C1
D
VD-A
UDIO(L)
VIDEO SIGNAL
AUDIO SIGNAL
LCD MODULE
ASSEMBL
Y
Q3016
BU
F
F
E
R
BU
F
F
E
R
Q3018
A18
A19
B19
B18
A17
B17
A20
B20
C17
D17
D21
E19
E20
D22
C21
C22
F19
F20
D16
Q3015
BU
F
F
E
R
BU
F
F
E
R
Q3020
D15
F2
J1
F1
AB22
SD-DQ(0-15)
SD-A(0-12)
IC3002
N4,P2,P4,R1-R4,T2,
T4,U4,V1,V4,W1-W3
W5,W7,AA4-AA8,
AB3-AB8
AA17
AB17
AA16
AB16
AA15
AB15
AA13
AA12
AA11
AB11
AB12
AB13
AA14
AB14
AB19
Y19
AA18
AB20
AA19
TP
POL
CPV
OE
STV
AC
L
K
AD
A
T
A1
BCLK
LRCLK
M2
L1
M1
L3