INTERCONNECT DRAWING
34
Figure 11: Speed Select Logic Input Wiring
52
54
12
53
11
S4
S3
S2
S1
48
S0
+24V
52
54
12
53
11
S4
S3
S2
S1
48
S0
+24V
ALTERNATE METHODS TO ACHIEVE PROGRESSIVE SPEED SELECT LOGIC
OR
PROGRESSIVELY
SCANNED RELAY LOGIC
USING DIODES (1N4003)
TO YIELD PROGRESSIVE INPUTS
WITH SINGLE RELAY CLOSURES
Summary of Contents for DSD 412
Page 1: ...DSD 412 DC Elevator Drive Technical Manual CS00407 rev 06...
Page 6: ...6...
Page 102: ...MAINTENANCE 102 Figure 24 Connector and E prom Locations...
Page 103: ...MAINTENANCE 103 Figure 25 Test Point Locations...
Page 115: ...OUTLINE DRAWING 100A 115 Figure 26 Drive Chassis Outline DSD 412 100 Amp...
Page 116: ...OUTLINE DRAWING 190A 116 Figure 27 Drive Chassis Outline DSD 412 195 Amp...
Page 117: ...OUTLINE DRAWING 300A 117 Figure 28 Drive Chasis Outline DSD 412 300 Amp...
Page 118: ...LAYOUT DRAWING 100A 118 Figure 29 Layout DSD 412 100 Amp A3 A1 A2 A2 L1 NEG GND L2 L3 POS...
Page 119: ...LAYOUT DRAWING 195A 119 Figure 30 Layout DSD 412 195 Amp A3 A1 A2 A2...
Page 120: ...LAYOUT DRAWING 300A 120 Figure 31 Layout DSD 412 300 Amp A3 A1 A2 A2...
Page 121: ......