FUNCTIONAL BLOCK DIAGRAM
[AK4458]
014011794-E-00
2015/01
- 5 -
4. Block Diagram and Functions
MCLK
SDTI1/DSDR1
LRCK/DSDL1
CAD0_I2C/CSN/DIF
BICK/DCLK
SCL/CCLK/TDM1
SDA/CDTI/TDM0
PDN
AVDD
Clock
Divider
DVSS
TVDD
PS/CAD0_SPI
AOUTR1N
VREFH1
VREFL1
AVSS
AOUTL1P
AOUTR1P
PCM
Data
Interface
De-empha
sis
DSD
Data
Interface
8X
Interpolator
Control
Register
SCF
SCF
AOUTR2N
VREFH2
VREFL2
AOUTL2P
AOUTL2N
AOUTR2P
Vref
SDTI2/DSDL2
8X
Interpolator
SCF
SCF
Vref
Bias
I2C
AOUTR3N
VREFH3
VREFL3
AOUTL3P
AOUTL3N
AOUTR3P
8X
Interpolator
SCF
SCF
AOUTR4N
VREFH4
VREFL4
AOUTL4P
AOUTL4N
AOUTR4P
Vref
8X
Interpolator
SCF
SCF
Vref
SDTI3/DSDR2/TDMO1
SDTI4/DSDL3/TDMO2
DSDR3
DSDL4
DSDR4
VDD18
LDO
DZF/SMUTE
CAD1/DCHAIN
LDOE
DATT
Soft Mute
DSD Filter
DATT
Soft Mute
DATT
Soft Mute
DSD Filter
DATT
Soft Mute
DATT
Soft Mute
DSD Filter
DATT
Soft Mute
DATT
Soft Mute
DSD Filter
DATT
Soft Mute
Modulator
Noise
Rejection
Filter
Modulator
Noise
Rejection
Filter
Modulator
Noise
Rejection
Filter
Modulator
Noise
Rejection
Filter
AOUTL1N
Figure 1. Block Diagram
PCM5100 (DIGITAL
:
IC321, IC322)
PCM5100 Block Diagram
PCM5100, PCM5101, PCM5102
SLAS764
–
MAY 2011
www.ti.com
DEVICE INFORMATION
TERMINAL FUNCTIONS, PCM510x
PCM510X (top view)
Table 2. TERMINAL FUNCTIONS, PCM510x
TERMINAL
I/O
DESCRIPTION
NAME
NO.
CPVDD
1
-
Charge pump power supply, 3.3V
CAPP
2
O
Charge pump flying capacitor terminal for positive rail
CPGND
3
-
Charge pump ground
CAPM
4
O
Charge pump flying capacitor terminal for negative rail
VNEG
5
O
Negative charge pump rail terminal for decoupling, -3.3V
OUTL
6
O
Analog output from DAC left channel
OUTR
7
O
Analog output from DAC right channel
AVDD
8
-
Analog power supply, 3.3V
AGND
9
-
Analog ground
DEMP
10
I
De-emphasis control for 44.1kHz sampling rate
(1)
: Off (Low) / On (High)
FLT
11
I
Filter select : Normal latency (Low) / Low latency (High)
SCK
12
I
System clock input
BCK
13
I
Audio data bit clock input
DIN
14
I
Audio data input
LRCK
15
I
Audio data word clock input
FMT
16
I
Audio format selection : I
2
S (Low) / Left justified (High)
XSMT
17
I
Soft mute control : Soft mute (Low) / soft un-mute (High)
LDOO
18
-
Internal logic supply rail terminal for decoupling
DGND
19
-
Digital ground
DVDD
20
-
Digital power supply, 3.3V
(1) Failsafe LVCMOS Schmitt trigger input
6
Copyright
©
2011, Texas Instruments Incorporated
A
udi
o
Int
er
fac
e
8x
Int
er
pol
at
ion
F
ilt
er
32b
it
∆
Σ
M
od
ul
at
or
Current
Segment
DAC
Current
Segment
DAC
I/V
I/V
A
na
lo
g
M
ut
e
A
na
lo
g
M
ut
e
Zero
Data
Detector
UVP/Reset
PLL Clock
Power
Supply
Ch. Pump
POR
Clock Halt
Detection
Advanced Mute Control
MCK
BCK
LRCK
C
A
P
P
C
A
P
M
V
N
E
G
LINE OUT
DIN (i2s)
PCM510x
CPVDD (3.3V)
AVDD (3.3V)
DVDD (3.3V)
GND
PCM5100, PCM5101, PCM5102
SLAS764
–
MAY 2011
www.ti.com
Table 1. Differences Between PCM510x Devices
Part Number
Dynamic Range
SNR
THD
PCM5102
112dB
112dB
–
93dB
PCM5101
106dB
106dB
–
92dB
PCM5100
100dB
100dB
–
90dB
spacer
Figure 1. PCM510x Functional Block Diagram
2
Copyright
©
2011, Texas Instruments Incorporated
68
Caution in
servicing
Electrical
Mechanical
Repair Information
Updating
