28
27
Pin Description
Pin
No
Symbol
I/O
Description
1 DVDD0
—
Digital power supply.
2 XRST
I
System reset. Reset when low.
3 MUTE
I
Mute input (low: off, high: on)
4 DATA
I
Serial data input from CPU.
5 XLAT
I
Latch input from CPU. Serial data is latched at the falling edge.
6 CLOK
I
Serial data transfer clock input from CPU.
7 SENS
O
1, 0
SENS output to CPU.
8 SCLK
I
SENS serial data readout clock input.
9 ATSK
I/O
1, 0
Anti-shock input/output.
10 WFCK
O
1, 0
WFCK output.
11 XUGF
O
1, 0
XUGF output. MNT0 or RFCK is output by switching with the command.
12 XPCK
O
1, 0
XPCK output. MNT1 is output by switching with the command.
13 GFS
O
1, 0
GFS output. MNT2 or XROF is output by switching with the command.
14 C2PO
O
1, 0
G2PO output. MNT3 or GTOP is output by switching with the command.
15 SCOR
O
1, 0
Outputs a high signal when either subcode sync S0 or S1 is detected.
16 C4M
O
1, 0
4.2336MHz output. 1/4 frequency division output for V16M in CAV-W mode or variable pitch mode.
17 WDCK
O
1, 0
Word clock output. f = 2Fs. GRSCOR is output by the command switching.
18 DVSS0
—
—
Digital GND.
19 COUT
I/O
1, 0
Track count signal I/O.
20 MIRR
I/O
1, 0
Mirror signal I/O.
21 DFCT
I/O
1, 0
Detect signal I/O.
22 FOK
I/O
1, 0
Focus OK signal I/O.
23 PWMI
I
Spindle motor external control input.
24 LOCK
I/O
1, 0
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples,
this pin outputs low. Input when LKIN = 1.
25 MDP
O
1, Z, 0
Spindle motor servo control output.
26 SSTP
I
Disc innermost track detection signal input.
27 FSTO
O
1, 0
2/3 frequency division output for XTAI pin.
28 DVDD1
—
—
Digital power supply.
29 SFDR
O
1, 0
Sled drive output.
30 SRDR
O
1, 0
Sled drive output.
31 TFDR
O
1, 0
Tracking drive output.
32 TRDR
O
1, 0
Tracking drive output.
33 FFDR
O
1, 0
Focus drive output.
34 FRDR
O
1, 0
Focus drive output.
35 DVSS1
—
—
Digital GND.
36 TEST
I
Test. Normally, GND.
37 TES1
I
Test. Normally, GND.
38 VC
I
Center voltage input.
39 FE
I
Focus error signal input.
40 SE
I
Sled error signal input.
41 TE
I
Tracking error signal input.
42 CE
I
Center servo analog input.
43 RFDC
I
RF signal input.
44 ADIO
O
Analog Test. No connected.
45 AVSS0
—
—
Analog GND.
46 IGEN
I
Constant current input for operational amplifi er.
47 AVDD0
—
—
Analog power supply.
48 ASYO
O
1, 0
EFM full-swing output. (low = Vss, high = VDD)
49 ASYI
I
Asymmetry comparator voltage input.
50 RFAC
I
EFM signal input.
51 AVSS1
—
—
Analog GND.
52 CLTV
I
Multiplier VCO1 control voltage input.
53 FILO
O
Analog Master PLL fi lter output (slave = digital PLL).
54 FILI
I
Master PLL fi lter input.
55 PCO
O
1, Z, 0
Master PLL charge pump output.
56 AVDD1
—
—
Analog power supply.
57 BIAS
I
Asymmetry circuit constant current input.
58 VCTL
I
Wide-band EFM PLL VCO2 control voltage input.
Wide-band EFM PLL VCO2 oscillation output. Serves as wide-band EFM
59 V16M
I/O
1, 0
PLL clock input by switching with the command.
60 VPCO
O
1, Z, 0
Wide-band EFM PLL charge pump output.
61 DVDD2
—
—
Digital power supply.
62 ASYE
I
Asymmetry circuit on/off (low = off, high = on).
63 MD2
I
Digital Out on/off control (low = off, high = on).
64 DOUT
O
1, 0
Digital Out output.
65 LRCK
O
1, 0
D/A interface. LR clock output. f = Fs
66 PCMD
O
1, 0
D/A interface. Serial data output (two's complement, MSB fi rst).
67 BCK
O
1, 0
D/A interface. Bit clock output. Outputs a high signal when the playback disc has emphasis, and a low
68 EMPH
O
1, 0
Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis.
69 XTSL
I
Crystal selection input. Low when the crystal is 16.9344MHz; high when it is 33.8688MHz.
70 DVSS2
—
—
Digital GND.
71 XTAI
I
Crystal oscillation circuit input. When the master clock is input externally,
input it from this pin.
72 XTAO
O
Crystal oscillation circuit output.
73 SOUT
O
1, 0
Serial data output in servo block.
74 SOCK
O
1, 0
Serial data readout clock output in servo block.
75 XOLT
O
1, 0
Serial data latch output in servo block.
76 SQSO
O
1, 0
Sub-Q 80-bit, PCM peak or level data outputs. CD TEXT data output.
77 SQCK
I
SQSO readout clock input.
78 SCSY
I
GRSCOR resynchronization input.
79 SBSO
O
1, 0
Sub-Q P to W serial output.
80 EXCK
I
SBSO readout clock input.
Notes)
PCMD is a MSB fi rst, two’s complement output.
XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection.
XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition
point coincide.
The GFS signal goes high when the frame sync and the insertion protection timing match.
C2PO represents the data error status.
Q116 : CXD3068Q
8. MICROPROCESSOR AND IC DATA
