154
GTXI User's Guide
register field names and bit numbers that are used by the field. Bit 0
is referred to here as the low-order bit.
Internal Address Register (IAR)
Bit #
15-
12
11-8 7
6-4 3
2-0
Function U V Bdis
PG
IAE
IA
Table D-1: IAR Bit Functions
U
Unused
V
Version (Buffer = 02h, Extender = 0Ah)
BDis
Buffer Disable. ‘0’ – buffer enabled (default). ‘1’ –
buffer disabled. If this bit is set the GTXI buffer and all
boards on carriers are disabled. This mode emits lower
levels of noise.
PG
Power Good status. These bits are read-only. Bit 4 is
power good of the controller side (right side). Bit 5 is
power good of the AUX side (Left side). Bit 6 is System
Ready for the GTXI with expanders.
IAE
Internal Address Enable. ‘0’ – IA disabled (default). ‘1’
– IA enabled. If this bit is cleared then no internal
register can be accessed.
IA
Internal Address (Bit 0 is LSB) as follows:
IA Name Description
Default
Value
0
IOM0
I/O Mask register 0
12 low order bits
x000
1
IOM1
I/O Mask register 0
12 low order bits
xx7C
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