Maverick EP7312, User Manual

Page 1: ...22 FAX 512 445 7581 http www cirrus com EP7312 User s Manual EP7312 USER S MANUAL Copyright 2000 Cirrus Logic Inc All Rights Reserved Note Cirrus Logic assumes no responsibility for the attached infor...

Page 2: ...available Advance product information describes products which are in development and subject to development changes Cirrus Logic Inc has made best efforts to ensure that the information contained in...

Page 3: ...3 2 Oscillator and PLL Test Mode 57 3 3 Debug ICE Test Mode 58 3 4 Hi Z System Test Mode 58 3 5 Software Selectable Test Functionality 58 PART II PIN AND REGISTER REFERENCE 4 PIN DESCRIPTIONS 60 4 1 E...

Page 4: ...7 2 PALLSW Least Significant Word LCD Palette Register 99 6 17 3 PALMSW Most Significant Word LCD Palette Register 99 6 17 4 FBADDR LCD Frame Buffer Start Address Register 100 6 18 SSI Registers 101 6...

Page 5: ...RO 116 6 23 4 9 Right Channel Transmit FIFO Not Full Flag RCNF 116 6 23 4 10 Right Channel Receive FIFO Not Empty Flag RCNE 116 6 23 4 11 Left Channel Transmit FIFO Not Full Flag LCNF 116 6 23 4 12 Le...

Page 6: ...Relationship Between Audio Clocks Clock Sources Sample Frequencies 41 Table 22 Matrix for Programming the MUX 42 Table 23 ADC Interface Operation Frequencies 44 Table 24 Instructions Supported in JTA...

Page 7: ...Table 56 DAI Control Register 106 Table 57 DAI64Fs Control Register 109 Table 58 Clock Source for 64 fs and 128 fs 109 Table 59 DAI Data Register 0 110 Table 60 DAI Data Register 1 111 Table 61 DAI Da...

Page 8: ...DS508UM1 9 Part I EP7312 User s Manual...

Page 9: ...ata Association JTAG Joint Test Action Group LCD liquid crystal display LED light emitting diode Table 1 Acronyms and Abbreviations LQFP low profile quad flat pack LSB least significant bit MIPS milli...

Page 10: ...ond kbyte kilobyte 1 024 bytes kHz kilohertz k kilohm Mbits s megabits 1 048 576 bits per second Mbyte megabyte 1 048 576 bytes MHz megahertz 1 000 kilohertz A microampere F microfarad W microwatt s m...

Page 11: ...number Numbers not indicated by an h 0x or single quotation marks are decimal Registers are referred to by acronym with bits listed in brackets separated by a hyphen for example CODR 0 7 The use of t...

Page 12: ...on to CD quality DACs and CODECs Interrupt controller Advanced system state control and power management Two full duplex 16550A compatible UARTs with 16 byte transmit and receive FIFOs IrDA SIR protoc...

Page 13: ...on of the various logic blocks that make up the pro cessor as well as all internal register information The URL Internet address for ARM technical manuals is http www arm com Documentation Manuals Fig...

Page 14: ...ected according to the state of the CLKENSL bit in the SYSCON2 register Table 4 on page 16 on the following page shows peripheral status in various power management states 2 2 1 Standby State The Stan...

Page 15: ...rom the Operating State the software will leave some interrupt sources enabled Note The CPU cannot be awakened by the TINT WEINT and BLINT interrupts when in the Standby State Address W B Operating Id...

Page 16: ...PU to start re ceiving its clock The CPU will still be held in reset at this point After the first clock is applied there will be a delay of about eight clock cycles before the CPU is enabled This del...

Page 17: ...reset state When the KBD6 bit SYSCON2 bit 1 is high only the lowest 6 bits of Port A are OR ed together to produce the internal wakeup signal and keyboard interrupt request The two most significant bi...

Page 18: ...r On Reset active low is the highest priority reset signal When active low it will reset all storage elements in the EP7312 nPOR active forces nSYSRES and nSTBY active nPOR will only be ac tive after...

Page 19: ...speed The address data will be fixed at 36 MHz The clock frequency used is select ed by programming the CLKCTL 1 0 bits in the SYSCON3 register The clock frequency selection does not effect the EPB e...

Page 20: ...the ARM720T and the address data buses both get clocked at 13 MHz The fixed clock sources to the various peripherals will have different frequencies than in the PLL mode In this configuration the PLL...

Page 21: ...IRQ sources Of these seventeen are mapped to the IRQ input and five sources are mapped to the FIQ input FIQs have a higher priority than IRQs If two interrupts are received from within the same group...

Page 22: ...upt input 1 nEINT 1 pin IRQ 6 EINT2 External interrupt input 2 nEINT 2 pin IRQ 7 EINT3 External interrupt input 3 EINT 3 pin IRQ 8 TC1OI TC1 underflow interrupt IRQ 9 TC2OI TC2 underflow interrupt IRQ...

Page 23: ...ansfer peripherals included in the EP7312 except for the master only SSI1 have local buffering to ensure a reasonable interrupt latency response requirement for the OS of 1 ms or less This assumes tha...

Page 24: ...than 1 s Including PLL osc settling time approx 0 25 sec or approx 500 s when in Idle State if in 13 MHz mode with CLKENSL set nEINT1 2 Not deglitched Worst case latency of 20 s Worst case 20 s if onl...

Page 25: ...cases following the de assertion of power on reset the EP7312 will be in the Standby State and requires a low to high transition on the external WAKEUP pin in order to actually start the boot sequenc...

Page 26: ...nal Page mode access is accomplished by setting SQAEN 1 which enables accesses of the form one random address followed by three sequential addresses etc while keeping nCS asserted These sequential bur...

Page 27: ...ccess sizes larger than a quad access multiple quad accesses are issued to the SDRAM The SDRAM controller can access a total memory size of 2 64 Mbytes Each individual SDRAM should be NEC or compatibl...

Page 28: ...4 Mbytes 8 Mbytes 16 Mbytes 32 Mbytes 64 Mbytes Den sity Mbits Width bits C R D C R D C R D C R D C R D 16 4 8 1 8 8 4 1 4 16 2 1 2 64 4 8 1 8 8 4 1 4 4 2 8 16 2 1 2 2 2 4 32 1 1 1 1 2 2 128 4 8 4 1...

Page 29: ...tes 8 Mbytes 16 Mbytes 32 Mbytes 64 Mbytes Den sity Mbits Width bits C R D C R D C R D C R D C R D C R D 16 4 4 1 4 8 2 1 2 16 1 1 1 64 4 4 1 4 4 2 8 8 2 1 2 2 2 4 16 1 1 1 1 2 2 128 4 4 1 4 8 2 1 2 2...

Page 30: ...Once the precharge is complete and the minimum tRP is satisfied the mode register can be pro grammed After the mode register set cycle tRSC 2 CLK minimum pause must be satisfied as well Only required...

Page 31: ...used to select the device to be accessed The space field is made directly from the A26 and A27 CPU address bits according to the decode shown in Table 16 on page 33 The size field is forced to 11 if...

Page 32: ...out or fails to complete for any other reason then the CL PS6700 will issue an interrupt i e a WR_FAIL interrupt In the case where the CL PS6700 write buffer is already full the PRDY signal will be de...

Page 33: ...6700 has support for DMA data transfers However DMA is supported only by software emu lation because the DMA address generator built into the EP7312 is dedicated to the LCD controller inter face If DM...

Page 34: ...of the serial interfaces will be used to describe each interface Pin definition information for the three multiplexed serial interfaces SSI2 DAI and CODEC and the ADC interface is described in Table 1...

Page 35: ...upt occurs the receive FIFO will be half full However it will not be possible to know how full the transmit FIFO will be since it was enabled at a later time Thus it is possible to unintentionally ove...

Page 36: ...cted to data lines 7 through 0 D 7 0 in this scheme In the big endian scheme the most significant byte of a word is stored at the lowest numbered byte and the least significant byte is stored at the h...

Page 37: ...44 dc dc 22 dc dc 33 dc dc 00000022 00000033 Word 2 B 11223344 dc 33 dc dc dc dc 22 dc 00000033 00000022 Word 3 B 11223344 44 dc dc dc dc dc dc 11 00000044 00000011 NOTE dc don t care Table 19 Effect...

Page 38: ...byte depth only i e like a conventional 16450 UART with double buffering The EP7312 also contains an IrDA Infrared Data Association SIR protocol encoder as a post processing stage on the output of UA...

Page 39: ...rammable from 8 48 Khz using either the on chip PLL 73 728MHz or the external 11 2896 Mhz clock The DAI interface contains separate transmit and receive FIFO s The transmit FIFO s are 8 audio samples...

Page 40: ...either the PLL or the external clock These fixed frequencies pass through a programmable divider net work which will create the appropriate values for SCLK LRCLK and MCLK for the desired sample fre q...

Page 41: ...ital audio data The remaining bits are output as zeros The LRCK signal is used as a frame synchronization signal Each transition of LRCK delineates the left and right halves of an audio sample When LR...

Page 42: ...the positive going edge of SCLK 2 15 2 ADC Interface Master Mode Only SSI1 Synchronous Serial Interface The first synchronous serial interface allows interfacing to the following peripheral devices In...

Page 43: ...d with low bandwidth inter faces such as for a touch screen ADC interface 2 15 3 Master Slave SSI2 Synchronous Serial Interface 2 A second SPI Microwire interface with full master slave capability is...

Page 44: ...sent MSB first and coincides with an appropriate frame sync pulse of one clock in du ration located one clock prior to the first data bit sent i e MSB It is not possible to send data LSB first When o...

Page 45: ...s read back 01 then the residual byte popped into the FIFO is valid and can be read back from the SS2DR register If the bits are not 01 then there has been another transmission received since the resi...

Page 46: ...transferred and will resume at least one clock prior to the first frame sync assertion To disable the clock the TX section is turned off In Master mode the EP7312 does not support the discontinuous cl...

Page 47: ...screen is mapped to the video frame buffer as one contiguous block where each horizontal line of pix els is mapped to a set of consecutive bytes or words in the video RAM The video frame buffer can be...

Page 48: ...omplex for 36 MHz mode of operation The total number of cycles 12 x 4 7 55 Thus 55 x 27 ns 1 49 s Figure 11 shows the organization of the video map for all combinations of bits per pixel The refresh r...

Page 49: ...nal peripherals The timer counters can operate in two modes free running or pre scale 2 17 1 Free Running Mode In the free running mode the counter will wrap around to 0xFFFF when it under flows and i...

Page 50: ...at the external pin is connected to an LED This module is driven from the RTCs 32 768 kHz oscillator and works in all running modes because no CPU intervention is needed once its rate and duty ratio h...

Page 51: ...is 0011 Note that it is only necessary to issue the SCAN_N instruction if the device is already in the JTAG mode The boundary scan chain is selected as the default on test logic reset and any of the...

Page 52: ...nto the ICE Breaker and the values currently appearing on the address bus data bus and the various control signals Any bit can be masked to remove it from the comparison Either unit can be programmed...

Page 53: ...1 EP7312 ADCCLK nADCCS ADCOUT ADCIN SMPCLK LEDDRV PHDIN RXD1 2 TXD1 2 DSR CTS DCD CS n WORD nCS 2 nCS 3 16 FLASH 16 FLASH 16 FLASH EXTERNAL MEMORY MAPPED EXPANSION BUFFERS BUFFERS AND LATCHES 16 FLASH...

Page 54: ...t triggered inputs and CMOS slew rate controlled output stages to reduce system noise Table 25 defines the I O buffer output characteristics which will apply across the full range of temperature and v...

Page 55: ...nTEST 1 0 In this mode all the internal oscillators and PLL are disabled and the appropriate crystal oscillator pins become the direct external oscillator inputs bypassing the oscillator and PLL MOSCI...

Page 56: ...This mode is only intended to allow test of the oscillators and PLL Note that these inputs are inverted before being passed to the PLL to ensure that the default state of the port all zero maps onto...

Page 57: ...sed by nCS 5 Hence nCS 5 takes on a dual role it will be active as the strobe for internal accesses and for any accesses to the standard address range for nCS 5 Additionally in this mode the internal...

Page 58: ...DS508UM1 59 Part II Pin and Register Reference...

Page 59: ...bus A 0 14 I O 15 bits of system byte address during memory and expansion cycles A 13 27 DRA 0 14 I O DRA 0 14 are multiplexed with A 13 27 offering additional power savings since the lightest loading...

Page 60: ...rnally decoded The encoding of these signals is as follows The core will generate an address When doing a read the ARM core will select the appropriate byte channels When doing a write the cor rect by...

Page 61: ...M nEXTFIQ I External active low fast interrupt request input EINT 3 I External active high interrupt request input nEINT 1 2 I Two general purpose active low interrupt inputs Power Management nPWRFL I...

Page 62: ...cted it forces the system into the Operating State from the Standby State It is only active when the system is in the Standby State This pin is ignored when the system is in the Idle or Operating Stat...

Page 63: ...I RS232 DCD input CTS I RS232 CTS input LCD DD 0 3 I O LCD serial display data pins can be used on power up to read the ID of some LCD modules See Table 31 on page 66 CL 1 O LCD line clock CL 2 O LCD...

Page 64: ...peration i e either the PLL or external 13 MHz clock mode PWM Drives DRIVE 0 1 I O PWM drive outputs These pins are inputs on power up to determine what polarity the output of the PWM should be when a...

Page 65: ...be monitored and hence provide more accurate control of timing or duration SSI2 CODEC DAI Direction Strength SSICLK PCMCLK SCLK I O 1 SSITXFR PCMSYNC LRCK I O 1 SSITXDA PCMOUT SDOUT Output 1 SSIRXDA...

Page 66: ...two CL PS6700 PC Card controllers are connected If this functionality is not required then the nCS 4 and nCS 5 memory is available The external boot ROM is not fully decoded i e the boot code will re...

Page 67: ...this range will not cause any external bus activity unless debug mode is enabled Writes to bits that are not explicitly defined in the internal area are legal and will have no effect Reads from bits...

Page 68: ...gister 1 0x8000 01C0 MEMCFG2 0 RW 32 Expansion memory configuration register 2 0x8000 0200 0 RW 32 Reserved 0x8000 0240 INTSR1 0 RD 32 Interrupt status register 1 0x8000 0280 INTMR1 0 RW 32 Interrupt...

Page 69: ...HALT WR Write to enter the Idle State 0x8000 0840 STDBY WR Write to enter the Standby State 0x8000 0880 0x8000 0FFF Reserved Write will have no effect read is undefined 0x8000 1000 FBADDR 0xC RW 4 LCD...

Page 70: ...22C0 LEDFLSH 0 RW 7 LED Flash register 0x8000 2300 SDCONF 2 RW 32 SDRAM Configuration Register 0x8000 2340 SDRFPR 128 RW 16 SDRAM Refresh Register 0x8000 2440 UNIQID 0 R 32 32 bit unique ID for the EP...

Page 71: ...cessarily the value written to it All bits are cleared by a system reset 6 1 2 PBDR Port B Data Register ADDRESS 0x8000 0001 Values written to this 8 bit read write register will be output on Port B p...

Page 72: ...system reset 6 1 5 PBDDR Port B Data Direction Register ADDRESS 0x8000 0041 Bits set in this 8 bit read write register will select the corresponding pin in Port B to become an output clearing a bit s...

Page 73: ...ng mode 5 TC1S Timer counter 1 clock source Setting this bit sets the TC1 clock source to 512 kHz clear ing it sets the clock source to 2 kHz 6 TC2M Timer counter 2 mode Setting this bit sets TC2 to p...

Page 74: ...processor are output on Port E bits 1 and 2 Note that these bits must be programmed to be outputs before this functionality can be observed The clock to the CPU is output on Port E Bit 0 to delineate...

Page 75: ...expansion slots that have external wait state generation enabled only 19 WAKEDIS Setting this bit disables waking up from the Standby State via the wakeup input 20 IRTXM IrDA TX mode bit This bit con...

Page 76: ...A s inputs irrespective of the state of the interrupt mask register This is called the Keyboard Direct Wakeup mode In this mode the inter rupt request does not have to get serviced If the interrupt i...

Page 77: ...13 MHz clock source mode Normally it will be set low however when set high it will cause a 500 kHz clock to be generated for the timers instead of the 541 kHz which would normally be available The di...

Page 78: ...and wait state scaling The table below lists the available options NOTE To determine the number of wait states programmed refer to Table 44 on page 88 and Table 45 on page 89 When operating at 13 MHz...

Page 79: ...our LCD data lines The state of the four LCD data lines is latched by the LCDEN bit and so it will always reflect the last state of these lines before the LCD controller was enabled 8 CTS This bit ref...

Page 80: ...ister is full If the FIFO is enabled the UTXFF bit will be set when the TX FIFO is full 24 CRXFE CODEC RX FIFO empty bit This will be set if the 16 byte CODEC RX FIFO is empty 25 CTXFF CODEC TX FIFO f...

Page 81: ...full This will get cleared when data is removed from the FIFO or the EP7312 is reset 5 SS2TXUF Master slave SSI2 TX FIFO Underflow bit This will be set if there is attempt to trans mit when TX FIFO i...

Page 82: ...ion NOTE WEINT is disabled during the Standby State Watch dog timer tick rate is 64 Hz in 13 MHz and 73 728 18 432 MHz modes Watchdog timer is turned off during the Standby State 3 MCINT Media changed...

Page 83: ...is disabled turned off during the Standby State 12 UTXINT1 Internal UART1 transmit FIFO half empty interrupt The function of this interrupt source depends on whether the UART1 FIFO is enabled If the F...

Page 84: ...FIFO contains fewer than 8 byte pairs This interrupt gets cleared by loading the FIFO with more data or disabling the TX One synchronization clock required when disabling the TX side before it takes e...

Page 85: ...se interfaces is enabled the configuration field for the appropriate chip select in the MEMCFG2 register is ignored When the PC CARD1 or 2 control bit in the SYSCON2 register is disabled then nCS 4 an...

Page 86: ...register Table 43 on page 88 defines the bus width field Note that the effect of this field is dependent on the two BOOTBIT bits that can be read in the SYSFLG1 register All bits in the memory config...

Page 87: ...ide bus access Low High 01 0 1 Reserved Low High 10 0 1 32 bit wide bus access Low High 11 0 1 16 bit wide bus access Low High 00 1 0 16 bit wide bus access High Low 01 1 0 32 bit wide bus access High...

Page 88: ...a longer sequential access In addition when this bit is not set non sequential accesses will have a single idle cycle inserted at least every four cycles so that the chip select is de asserted periodi...

Page 89: ...a register is a 16 bit read write register which sets and reads data to TC2 Any value written will be decremented on the next rising edge of the clock 6 5 3 RTCDR Real Time Clock Data Register ADDRESS...

Page 90: ...100 05 11 1100 13 03 0101 06 10 1101 14 02 0110 07 09 1110 15 01 0111 08 08 1111 16 00 continually on Table 48 LED Duty Ratio 31 11 10 9 8 7 6 5 4 2 1 0 Reserved SDACTIVE CLKCTL SDWIDTH SDSIZE Reserve...

Page 91: ...d to implement the MaverickKey functionality and to create 32 bit unique SDMI assigned IDs The unique number is read only and cannot be modified by software 6 10 RANDID0 Register 8000 2700 This 32 bit...

Page 92: ...D3 Register 8000 2708C This 32 bit register is set at the factory and is used to implement the MaverickKey functionality and to create 128 bit unique random IDs The unique number is read only and cann...

Page 93: ...it field controls the on time for the Drive 0 PWM pump while the system is powered from batteries Setting these bits to 0 disables this pump while setting these bits to 1 allows the pump to be driven...

Page 94: ...the last byte received by the UART If it is enabled data received and error status is automatically pushed onto the RX FIFO The RX FIFO is 10 bits wide by 16 deep Note These registers should be acces...

Page 95: ...me example bit rates with the corresponding divisor value In 13 MHz mode the clock frequency fed to the UART is 1 8571 MHz In this mode zero is a legal divisor value and will generate the maximum poss...

Page 96: ...Video buffer size Bit Description 0 12 Video buffer size The video buffer size field is a 13 bit field that sets the total number of bits x 128 quad words in the video display buffer This is calculate...

Page 97: ...fter every CL 1 high pulse this refresh fre quency is only an approximation the accurate formula is 12 288E6 640x240 120 79 937 Hz 25 29 AC prescale The AC prescale field is a 5 bit number that sets t...

Page 98: ...age 100 Note that colors 8 15 are the inverse of colors 7 0 respectively This means that colors 7 and 8 are identical Therefore in reality only 15 grayscales available not 16 The steps in the grayscal...

Page 99: ...t where the frame buffer is located On reset this will be set to 0xC The register is 4 bits wide bits 0 3 This register must only be reprogrammed when the LCD is disabled i e setting the LCDEN bit wit...

Page 100: ...the end of a transfer the SSEOTI interrupt will be asserted To clear the interrupt the SYNCIO register must be read The data read from the SYNCIO register is the last sixteen bits shifted out of the A...

Page 101: ...N3 register 0 this is the 8 bit configuration data to be sent to the ADC When the ADCCON control bit in the SYSCON3 register 1 this field determines the length of the ADC configuration data held in th...

Page 102: ...ocation will clear the RTC match interrupt 6 20 7 UMSEOI UART1 Modem Status Changed End of Interrupt ADDRESS 0x8000 0780 A write to this location will clear the modem status changed interrupt 6 20 8 C...

Page 103: ...no effect 6 22 SS2 Registers 6 22 1 SS2DR Synchronous Serial Interface 2 Data Register ADDRESS 0x8000 1500 This is the 16 bit wide data register for the full duplex master slave SSI2 synchronous seri...

Page 104: ...ta register addresses the top of the Right Channel Transmit FIFO and the bottom of the Right Channel Receive FIFO A read accesses the receive FIFOs and a write the transmit FIFOs Note that these are f...

Page 105: ...IFO Interrupt Mask 0 Left Channel Transmit FIFO half full or less condition does not generate an interrupt LCTS bit ignored 1 Left Channel Transmit FIFO half full or less condition generates an interr...

Page 106: ...t mask LCTM bit is used to mask or enable the left channel sample transmit FIFO service request interrupt When LATM 0 the interrupt is masked and the state of the Left Channel Transmit FIFO service re...

Page 107: ...e of the Right Channel Receive FIFO service request RCRS bit within the DAI status register is ignored by the interrupt controller When RCRM 1 the interrupt is enabled and whenever RCRS is set one an...

Page 108: ...d 1 AUDCLKEN Enable audio clock generator 2 AUDCLKSRC Clock Source 0 73 728 MHz PLL 1 11 2896 MHz External Clock 3 MCLK256EN Selects MCLK 256 fs or the BUZZ pin 4 Reserved 5 LOOPBACK Test mode Loops d...

Page 109: ...and all remaining values within the FIFO automatically transfer down one location When DAIDR0 is written the top most entry of the Right Channel Transmit FIFO is accessed After a write data is automat...

Page 110: ...write data is automatically transferred down to the lowest location within the transmit FIFO which does not already contain valid data Data is removed from the bottom of the FIFO one value at a time...

Page 111: ...FIFO is enabled by writing 0x0011 8000 and disabled by writing 0x0011 0000 After writing a value to this register wait until the FIFO operation complete bit FIFO is set in the DAI status register bef...

Page 112: ...31 13 12 11 10 9 8 7 Reserved FIFO LCNE LCNF RCNE RCNF RCCELCRO 6 5 4 3 2 1 0 RCNFLCTU LCRORCRO LCTURCTU LCRS LCTS LCRSRCRS LCTSRCTS Bit Description 0 RCTS Right Channel Transmit FIFO Service Request...

Page 113: ...ed an overrun 1 Left Channel Receive logic attempted to place data into receive FIFO while it was full request interrupt 8 RCNF Right Channel Transmit FIFO Not Full read only 0 Right Channel Transmit...

Page 114: ...est is made unless the Left Channel Transmit FIFO interrupt request mask LCTM bit is cleared After the CPU fills the FIFO such that four or more locations are filled within the Left Channel Transmit F...

Page 115: ...l This bit can be polled when using programmed I O to fill the Right Channel Transmit FIFO This bit does not request an interrupt 6 23 4 10 Right Channel Receive FIFO Not Empty Flag RCNE The Right Cha...

Page 116: ...E NSDWE NMOE NSDCAS NCS 0 NCS 1 NCS 2 NCS 3 D 7 A 7 D 8 A 8 D 9 D 10 A 10 VSSIO VDDIO A 11 D 12 A 12 D 13 A 13 DRA 14 D 14 DD 3 D 17 D 15 A 17 DRA 10 NTRST VSSIO VDDIO D 18 A 18 DRA 9 D 19 A 19 DRA 8...

Page 117: ...PBGA PIN DIAGRAM Figure 15 256 Ball Plastic Ball Grid Array Diagram A B C D E F G H J K L M N P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 256 Ball PBGA Bottom View Note For package specifications ple...

Page 118: ...E 00000020 13A0000B MOVNE r0 Hw_BR9600_13 Load 13 MhZ value if bit set 00000024 03A00017 MOVEQ r0 Hw_BR9600 If not set load other divisor 00000028 E3800806 ORR r0 r0 Hw_WRDLEN8 Insert 8 bit character...

Page 119: ...068 00000068 00000068 00000068 00000068 E28CAB09 ADD r10 r12 WWWWWWWWWW R10 0x80002400 also XXXXXX 0000006C E58AC080 STR r12 r10 ZZZZZZZZZZZ YYYYYYYYYY 00000070 E248FB02 SUB pc r8 ImageSize Branch to...

Page 120: ...in descriptions 60 pin descriptions external signal functions 60 pin diagram 117 pin diagrams 208 pin LQFP 117 256 pin PBGA 118 pin information A 60 61 ADCCLK 64 ADCIN 64 ADCOUT 64 BA 61 BATOK 62 BOOT...

Page 121: ...Real Time Clock Data Register 90 RTCMR Real Time Clock Data Register 90 SS2 104 SS2DR Synchronous Serial Interface 2 Data Register 104 SS2POP Synchronous Serial Interface 2 Pop Residual Byte 104 state...

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