82
DS508UM1
6.2.5
SYSFLG2 — System Status Register 2
ADDRESS: 0x8000.1140
The bits of the second system status register are defined in Table 39.
23
22
21-12
11
10-7
6
UTXFF2
URXFE2
Reserved
UBUSY2
Reserved
CKMODE
5
4
3
2
1
0
SS2TXUF
SS2TXFF
SS2RXFE
RESFRM
RESVAL
SS2RXOF
Bit
Description
0
SS2RXOF: Master / slave SSI2 RX FIFO overflow. This bit is set when a write is attempted to a
full RX FIFO (i.e., when RX is still receiving data and the FIFO is full). This can be cleared in one
of two ways:
1. Empty the FIFO (remove data from FIFO) and then write to SRXEOF location.
2. Disable the RX (affects of disabling the RX will not take place until a full SSI2 clock
cycle after it is disabled)
1
RESVAL: Master / slave SSI2 RX FIFO residual byte present, cleared by popping the residual
byte into the SSI2 RX FIFO or by a new RX frame sync pulse.
2
RESFRM: Master / slave SSI2 RX FIFO residual byte present, cleared only by a new RX frame
sync pulse.
3
SS2RXFE: Master / slave SSI2 RX FIFO empty bit. This will be set if the 16 x 16 RX FIFO is
empty.
4
SS2TXFF: Master / slave SSI2 TX FIFO full bit. This will be set if the 16 x 16 TX FIFO is full. This
will get cleared when data is removed from the FIFO or the EP7312 is reset.
5
SS2TXUF: Master / slave SSI2 TX FIFO Underflow bit. This will be set if there is attempt to trans-
mit when TX FIFO is empty. This will be cleared when FIFO gets loaded with data.
6
CKMODE: This bit reflects the status of the CLKSEL (PE[2]) input, latched during nPOR. When
low, the PLL is running and the chip is operating in 18.432–73.728 MHz mode. When high the
chip is operating from an external 13 MHz clock.
11
UBUSY2: UART2 transmitter busy. This bit is set while UART2 is busy transmitting data; it is
guaranteed to remain set until the complete byte has been sent, including all stop bits.
22
URXFE2: UART2 receiver FIFO empty. The meaning of this bit depends on the state of the UFI-
FOEN bit in the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set
when the RX holding register contains is empty. If the FIFO is enabled, the URXFE bit will be set
when the RX FIFO is empty.
23
UTXFF2: UART2 transmit FIFO full. The meaning of this bit depends on the state of the UFI-
FOEN bit in the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set
when the TX holding register is full. If the FIFO is enabled, the UTXFF bit will be set when the TX
FIFO is full.
Table 39. SYSFLG2
Summary of Contents for EP7312
Page 8: ...DS508UM1 9 Part I EP7312 User s Manual...
Page 58: ...DS508UM1 59 Part II Pin and Register Reference...
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