DS508UM1
113
6.23.4
DAISR — DAI Status Register
ADDRESS: 0x8000.2100
The DAI Status Register (DAISR) contains bits which signal FIFO overrun and underrun errors and
FIFO service requests. Each of these conditions signal an interrupt request to the interrupt controller.
The status register also flags when transmit FIFOs are not full, when the receive FIFOs are not empty,
when a FIFO operation is complete, and when the right channel or left channel portion of the CODEC
is enabled (no interrupt generated).
Bits which cause an interrupt signal the interrupt request as long as the bit is set. Once the bit is
cleared, the interrupt is cleared. Read / write bits are called status bits, read-only bits are called flags.
Status bits are referred to as “sticky” (once set by hardware, they must be cleared by software). Writ-
ing a one to a sticky status bit clears it, while writing a zero has no effect. Read-only flags are set and
cleared by hardware, and writes have no effect. Additionally, some bits which cause interrupts have
corresponding mask bits in the control register and are indicated in the section headings below. Note
that the user has the ability to mask all DAI interrupts by clearing the DAI bit within the interrupt con-
troller mask register INTMR3.
31-13
12
11
10
9
8
7
Reserved
FIFO
LCNE
LCNF
RCNE
RCNF
RCCELCRO
6
5
4
3
2
1
0
RCNFLCTU
LCRORCRO
LCTURCTU
LCRS
LCTS
LCRSRCRS
LCTSRCTS
Bit
Description
0
RCTS: Right Channel Transmit FIFO Service Request Flag (read-only)
0 — Right Channel Transmit FIFO is more than half full (five or more entries filled) or DAI dis-
abled
1 — Right Channel Transmit FIFO is half full or less (four or fewer entries filled) and DAI oper-
ation is enabled, interrupt request signaled if not masked
(if RCTM = 1)
1
RCRS: Right Channel Receive FIFO Service Request (read-only)
0 — Right Channel Receive FIFO is less than half full (five or fewer entries filled) or DAI dis-
abled
1 — Right Channel Receive FIFO is half full or more (six or more entries filled) and DAI opera-
tion is enabled, interrupt request signaled if not masked (if RCRM = 1)
2
LCTS: Left Channel Transmit FIFO Service Request Flag (read-only)
0 — Left Channel Transmit FIFO is more than half full or less (four or fewer entries filled) or DAI
disabled.
1 — Left Channel Transmit FIFO is half full or less (four or fewer entries filled) and DAI opera-
tion is enabled, interrupt request signaled if not masked
(if LCTM = 1)
3
LCRS: 0 — Left Channel Receive FIFO is less than half full (five or fewer entries filled) or DAI
disabled.
1 — Left Channel Receive FIFO is half full or more (six or more entries filled) and DAI opera-
tion is enabled, interrupt request signalled if not masked (if LCRM = 1)
Table 62.
DAI
Control, Data and Status Register Locations
Summary of Contents for EP7312
Page 8: ...DS508UM1 9 Part I EP7312 User s Manual...
Page 58: ...DS508UM1 59 Part II Pin and Register Reference...
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