DS508UM1
83
6.3
Interrupt Registers
6.3.1
INTSR1 — Interrupt Status Register 1
ADDRESS: 0x8000.0240
The interrupt status register is a 32-bit read only register. The interrupt status register reflects the cur-
rent state of the first 16 interrupt sources within the EP7312. Each bit is set if the appropriate interrupt
is active. The interrupt assignment is given in Table 40.
15
14
13
12
11
10
9
8
SSEOTI
UMSINT
URXINT1
UTXINT1
TINT
RTCMI
TC2OI
TC1OI
7
6
5
4
3
2
1
0
EINT3
EINT2
EINT1
CSINT
MCINT
WEINT
BLINT
EXTFIQ
Bit
Description
0
EXTFIQ: External fast interrupt. This interrupt will be active if the nEXTFIQ input pin is forced low and is
mapped to the FIQ input on the ARM720T processor.
1
BLINT: Battery low interrupt. This interrupt will be active if no external supply is present (nEXTPWR is
high) and the battery OK input pin BATOK is forced low. This interrupt is de-glitched with a 16 kHz clock,
so it will only generate an interrupt if it is active for longer than 125
µ
sec. It is mapped to the FIQ input
on the ARM720T processor and is cleared by writing to the BLEOI location.
NOTE:
BLINT is disabled during the Standby State.
2
WEINT: Tick Watch dog expired interrupt. This interrupt will become active on a rising edge of the peri-
odic 64 Hz tick interrupt clock if the tick interrupt is still active (i.e., if a tick interrupt has not been ser-
viced for a complete tick period). It is mapped to the FIQ input on the ARM720T processor and the TEOI
location.
NOTE:
WEINT is disabled during the Standby State.
Watch dog timer tick rate is 64 Hz (in 13 MHz and 73.728–18.432 MHz modes).
Watchdog timer is turned off during the Standby State.
3
MCINT: Media changed interrupt. This interrupt will be active after a rising edge on the nMEDCHG input
pin has been detected, This input is de-glitched with a 16 kHz clock so it will only generate an interrupt
if it is active for longer than 125
µ
sec. It is mapped to the FIQ input on the ARM7TDMI processor and is
cleared by writing to the MCEOI location. On power-up, the Media change pin (nMEDCHG) is used as
an input to force the processor to either boot from the internal Boot ROM, or from external memory.
After power-up, the pin can be used as a general purpose FIQ interrupt pin.
4
CSINT: CODEC sound interrupt, generated when the data FIFO has reached half full or empty (depend-
ing on the interface direction). It is cleared by writing to the COEOI location.
5
EINT1: External interrupt input 1. This interrupt will be active if the nEINT1 input is active (low). It is
cleared by returning nEINT1 to the passive (high) state.
6
EINT2: External interrupt input 2. This interrupt will be active if the nEINT2 input is active (low). It is
cleared by returning nEINT2 to the passive (high) state.
7
EINT3: External interrupt input 3. This interrupt will be active if the EINT3 input is active (high). It is
cleared by returning EINT3 to the passive (low) state.
8
TC1OI: TC1 under flow interrupt. This interrupt becomes active on the next falling edge of the timer
counter 1 clock after the timer counter has under flowed (reached zero). It is cleared by writing to the
TC1EOI location.
Table 40. INTSR1
Summary of Contents for EP7312
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