MAX32600 User’s Guide
Communication Peripherals
7.2 SPI
Figure 7.6: SPI Clock Polarity
The low bit of the spi_mode field controls the clock phase. The SPI clock phase is used to determine when data is sampled and valid on the MISO/MOSI lines.
The default setting is rising edge as shown in the figure below labeled CLK Phase = 0. To set the clock phase to be active on the falling edge of the clock, set the
spi_mode lower bit to a 1.
Rev.1.3 April 2015
Maxim Integrated
Page 265