MAX32600 User’s Guide
Flash Controller and Instruction Cache
14.1 Registers (FLC)
14.1.1.13
FLC_INTEN1
FLC_INTEN1.sram_addr_wrapped
Field
Bits
Default
Access
Description
sram_addr_wrapped
0
0
W1C
SRAM
Address
Wrapped
Interrupt
Enable/Disable
FLC_INTEN1.invalid_flash_addr
Field
Bits
Default
Access
Description
invalid_flash_addr
1
0
W1C
Invalid Flash Address Interrupt Enable/
−
Disable
FLC_INTEN1.flash_read_locked
Field
Bits
Default
Access
Description
flash_read_locked
2
0
W1C
Flash Read from Locked Area Interrupt
Enable/Disable
FLC_INTEN1.trim_update_done
Field
Bits
Default
Access
Description
trim_update_done
3
0
W1C
Trim Update Complete Interrupt Enable/
−
Disable
14.1.1.14
FLC_DISABLE_XR0
Rev.1.3 April 2015
Maxim Integrated
Page 663