MAX32600 User’s Guide
System Clock, Timers/Counters, Watchdog Timers and Real Time Clock
10.2 Watchdog Timers
• Eh: 2
17
• Fh: 2
16
WDTn_CTRL.rst_period
Field
Bits
Default
Access
Description
rst_period
7:4
.
R/W
Period from WDT Clear to Reset Flag Set
Reset Period - the time period from the beginning of the watchdog timer count (WDT is cleared to zero by being enabled or when the watchdog timer is cleared by
writing to the CLEAR register) until the Watchdog Reset Flag is set.
Defined in terms of a number of watchdog clocks, with the number of clocks given by 2
N
, N=(31 - field value), e.g.
• 0h: 2
31
• 1h: 2
30
• 2h: 2
29
• ....
• Eh: 2
17
• Fh: 2
16
WDTn_CTRL.en_timer
Field
Bits
Default
Access
Description
en_timer
8
.
R/W
Watchdg Timer Enable
• 0: Watchdog timer is disabled and the counter is held at zero.
• 1: Watchdog timer is enabled and counting.
Rev.1.3 April 2015
Maxim Integrated
Page 559
