PCI-2515 User's Guide
Specifications
29
Counters
Counter inputs can be scanned based on an internal programmable timer or an external clock source.
Table 5. Counter specifications
Channels 4
independent
Resolution 32-bit
Input frequency
20 MHz maximum
Input signal range
-5 V to 10 V
Input characteristics
10
k
Ω
pull-up, ±15 kV ESD protection
Trigger level
TTL
Minimum pulse width
25 ns high, 25 ns low
De-bounce times
16 selections from 500 ns to 25.5 ms, positive or negative edge sensitive, glitch
detect mode or de-bounce mode
Time-base accuracy
30 ppm (0 ° to 50 °C)
Counter read pacer
Onboard clock, external clock (XAPCR)
Trigger sources and modes
Programmable mode
Counter
Counter mode options
Totalize, clear on read, rollover, stop at all Fs, 16-bit or 32-bit, any other channel
can gate the counter
Input sequencer
Analog, digital, and counter inputs can be scanned based on either an internal programmable timer or an
external clock source.
Table 6. Input sequencer specifications
Scan clock sources: two (Note 3)
Internal:
Analog channels from 1 µs to 1 sec in 20.83 ns steps.
Digital channels and counters from 83.33 ns to 1 sec in 20.83 ns
steps.
External. TTL-level input:
Analog channels down to 1 µs minimum
Digital channels and counters down to 83 ns minimum
Programmable parameters per scan:
Programmable channels (random order), programmable gain
Depth 512
locations
Onboard channel-to-channel scan rate
Analog: 1 MHz maximum
Digital: 12 MHz
External acquisition scan clock input maximum
rate
1.0 MHz
Clock signal range:
Logical zero: 0 V to 0.8 V
Logical one: 2.4 V to 5.0 V
Minimum pulse width
50 ns high, 50 ns low
Note 3:
The maximum scan clock rate is the inverse of the minimum scan period. The minimum scan period
is equal to 1 µs times the number of analog channels. If a scan contains only digital channels then
the minimum scan period is 83 ns times the number of digital channels.
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