MD8000
Rev. H
MD8000 SWCNT-9 Controller Module
3-3.3
Block Diagram
Figure 3-3.2 is a block diagram of the SWCNT-9 board and explanatory legend.
Figure 3-3.2: SWCNT-9 Block Diagram
Name
Description
PowerPC
Host CPU: PowerQUICC
TM
IIPro
PLD&FPGA
PLD (Programmable Logic Device): MAXII Logic
FPGA (Field Programmable
: CycloneII Logic
DDR2 SDRAM
MAIN Memory (PowerPC work memory)
Boot Flash
PowerPC Boot Flash Memory
Data Flash
FPGA Configuration Data Flash Memory
SDC
SD Card Controller
LANC
10/100BASE-TX Ethernet Controller
E1/T1 Framer
External clock extraction
PT
10/100BASE-TX Pulse Trance
E1/T1 Pulse Trance
Sync CLK CLT
& Division
External clock synchronization control and delivery to Channel
boards
L2SW
AXEL-X Layer 2 Switch
1G-PHY
1G-Serial connection to the other SWCNT for HA (High Availability)
communication path between AXEL-Xs and between PowerPCs
ADBUS I/F
SWCNT address bus interface
PowePC
LANC
Mother
board
ETHER
ADBUS
I/F
PT
L2SW
Sync CLK
CTL
&
Division
E1/T1
Framer
XAUI
10G
9
1G
PHY
HA : High Availability
BB
Ex-CLK
HA
BU
S
SDC
SD
Card
nvSRAM
Boot
Flash
PT
PLD
&
FPGA
BUS
Data
Flash
DDR2
SDRAM
Summary of Contents for MD8000 Series
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