MeiG
Product
Manual
of
SLM750
Module
SLM750
Module
Hardware
Design
Page 22, total 84 pages
V
IH
min=1.2V
V
IH
max=2.0V
If unused, keep
it open.
PCM_OUT
25
DO
PCM data output
V
OL
max=0.45V
V
OH
min=1.35V
1.8V power
domain.
If unused, keep
it open.
PCM_CLK 27
IO
PCM
clock
V
OL
max=0.45V
V
OH
min=1.35V
V
IL
min=-0.3V
V
IL
max=0.6V
V
IH
min=1.2V
V
IH
max=2.0V
1.8V power
domain. In master
mode, it is an
output signal. In
slave mode, it is an
input signal. If
unused, keep it
open.
PCM_SYNC 26 IO PCM
data
synchronous
signal
V
OL
max=0.45V
V
OH
min=1.35V
V
IL
min=-0.3V
V
IL
max=0.6V
V
IH
min=1.2V
V
IH
max=2.0V
1.8V power
domain. In master
mode, it is an
output signal. In
slave mode, it is an
input signal. If
unused, keep it
open.
CDC_I2S_MC
LK
116 DO
19.2MHz
signal
clock
Module
outputs19.2MHz
clock signal, which is
used to provide to the
external CODEC,
If
unused, keep it
open.
I2C interface
Pin name
Pin
number
I/O
Description
DC features
Note
I2C_SCL
41 OD
I2C serial clock
Require
external pull-up to
1.8V. If unused,
keep it open.
I2C_SDA
42 OD
I2C serial data
Require
external pull-up to
1.8V. If unused,
keep it open.
RF Interface
Pin name
Pin
number
I/O
Description
DC features
Note
ANT_DIV
35 AI
Diversity antenna
50 ohm
impedance
If unused, keep it
open.
ANT_MAIN
49 IO
Main antenna
50 ohm