MeiG
Product
Manual
of
SLM750
Module
SLM750
Module
Hardware
Design
Page 47, total 84 pages
on the rising edge; the PCM_SYNC rising edge represents the more significant bit. The mode only
supports 128 kHz PCM_CLK and 8kHz, 50% duty cycle PCM_SYNC.
SLM750 supports 8-bit A-law, u-law and 16-bit linear encoding formats. The following figures
show the timing relationship in short frame mode with PCM_SYNC=8 kHz and
PCM_CLK=2048kHz, as well as the timing relationship in long frame mode with PCM_SYNC=8
kHz and PCM_CLK=128kHz.
Figure 18 Timing in short frame mode
Figure 19 Timing in long frame mode
