KS8995MA Evaluation Board User’s Guide
Micrel Inc. Confidential
Page 30
11/3/2006
8.0 PCB Layout Guideline for ESD and EMI
ESD and EMI (FCC) are basically the same problem for the system design. ESD is
absorbing energy and EMI is emitting energy. If your PC board has low EMI, it is
probably ESD proof as well.
All high-speed signals must have an unbroken reference ground plane.
A minimum 6 layer PCB is recommended for FCC compliance. The layer stacking could
be as follows:
________________ layer 1 component side (short traces)1 oz copper
________________ layer 2 power plane 2 oz copper
________________ layer 3 GND plane 2 oz copper
________________ layer 4 signal 5 mil trace /10 mil spacing 1 oz copper
________________ layer 5 signal 5 mil trace /10 mil spacing 1 oz copper
________________ layer 6 GND signal 1 oz copper
Differential pair is 5mil trace/5mil spacing.
Very few signal traces are exposed to the outside, except the short traces from device pins to
internal layers. This will improve ESD, EMI and signal integrity.
A 4 layer PCB is not recommended for FCC compliance, but if that is the only option
available, use the following layer stacking:
________________ layer 1 component side 1 oz copper
______5mil______ layer 2 GND plane 1 oz copper
________________ layer 3 power plane 1 oz copper
______5mil______ layer 4 signal oz copper
The thickness between layer 1 and 2 is 5mil, the thickness between layer 3 and 4 is 5 mils.
The following are the PCB layout guidelines:
1. Keep the Transmit differential pair on component side and Receive pairs on another
layer. Route the differential pairs close together, 5mil/5mil space (parallel) and
minimum 20 mil away from other signals.
2. Route Clock traces directly above an unbroken Ground plane and keep 2X trace width
away from other signal traces. Add damping resistor (33 to 50 OHM) at Clock output.
3. Keep all signal traces inside the unbroken ground plane (in different layer).
4. The ground nets are all common.
5. Void power and ground planes directly under the magnetic.
6. Use bulk capacitors 47uf to 100uf between power and ground planes on each corner of
MICREL/KENDIN chip.
7. Each power pin should have a 0.1uf de-coupling cap close to the power pin, and drop
via near the cap side.
8. Brake the ground loop in certain locations to avoid loop antenna effect.
9. Poorly regulated or over-burdened power supply will generate digital switching noise.
