Microchip Technology dsPIC30F6010 Datasheet Download

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dsPIC30F6010

DS70119B-page 144

Advance Information



2004 Microchip Technology Inc.

21.4

Watchdog Timer (WDT)

21.4.1

WATCHDOG TIMER OPERATION

The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software mal-
function. The WDT is a free running timer, which runs
off an on-chip RC oscillator, requiring no external com-
ponent. Therefore, the WDT timer will continue to oper-
ate even if the main processor clock (e.g., the crystal
oscillator) fails.

21.4.2

ENABLING AND DISABLING THE
WDT

The Watchdog Timer can be “Enabled” or “Disabled”
only through a configuration bit (FWDTEN) in the
configuration register FWDT.

Setting FWDTEN =

enables the Watchdog Timer.

The enabling is done when programming the device.
By default, after chip-erase, FWDTEN bit =

. Any

device programmer capable of programming
dsPIC30F devices allows programming of this and
other configuration bits.

If enabled, the WDT will increment until it overflows or
“times out”. A WDT time-out will force a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a

CLRWDT

instruction.

If a WDT times out during Sleep, the device will wake-
up. The WDTO bit in the RCON register will be cleared
to indicate a wake-up resulting from a WDT time-out.

Setting FWDTEN =

allows user software to enable/

disable the Watchdog Timer via the SWDTEN
(RCON<5>) control bit.

21.5

Low Voltage Detect

The Low Voltage Detect (LVD) module is used to detect
when the V

of the device drops below a threshold

value V

LVD

, which is determined by the LVDL<3:0> bits

(RCON<11:8>) and is thus user-programmable. The
internal voltage reference circuitry requires a nominal
amount of time to stabilize, and the BGST bit
(RCON<13>) indicates when the voltage reference has
stabilized.

In some devices, the LVD threshold voltage may be
applied externally on the LVDIN pin.

The LVD module is enabled by setting the LVDEN bit
(RCON<12>).

21.6

Power Saving Modes

There are two power saving states that can be entered
through the execution of a special instruction,

PWRSAV

These are: Sleep and Idle.

The format of the

PWRSAV

instruction is as follows:

PWRSAV <parameter>

, where ‘

parameter

’ defines

Idle or Sleep mode.

21.6.1

SLEEP MODE

In Sleep mode, the clock to the CPU and peripherals is
shutdown. If an on-chip oscillator is being used, it is
shutdown.

The fail-safe clock monitor is not functional during
Sleep, since there is no clock to monitor. However,
LPRC clock remains active if WDT is operational during
Sleep.

The Brown-out protection circuit and the Low Voltage
Detect circuit, if enabled, will remain functional during
Sleep.

The processor wakes up from Sleep if at least one of
the following conditions has occurred:

• any interrupt that is individually enabled and

meets the required priority level

• any Reset (POR, BOR and MCLR)

• WDT time-out

On waking up from Sleep mode, the processor will
restart the same clock that was active prior to entry
into Sleep mode. When clock switching is enabled,
bits COSC<1:0> will determine the oscillator source
that will be used on wake-up. If clock switch is
disabled, then there is only one system clock.

If the clock source is an oscillator, the clock to the
device will be held off until OST times out (indicating a
stable oscillator). If PLL is used, the system clock is
held off until LOCK =

(indicating that the PLL is sta-

ble). In either case, T

POR

, T

LOCK

and T

PWRT

delays are

applied.

If EC, FRC, LPRC or EXTRC oscillators are used, then
a delay of T

POR

(~ 10

s) is applied. This is the smallest

delay possible on wake-up from Sleep.

Moreover, if LP oscillator was active during Sleep, and
LP is the oscillator used on wake-up, then the start-up
delay will be equal to T

POR

PWRT delay and OST

timer delay are not applied. In order to have the small-
est possible start-up delay when waking up from Sleep,
one of these faster wake-up options should be selected
before entering Sleep.

Note:

If a POR or BOR occurred, the selection of
the oscillator is based on the FOS<1:0>
and FPR<3:0> configuration bits.