Microchip Technology dsPIC30F6010 Datasheet Download

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dsPIC30F6010

DS70119B-page 32

Advance Information



2004 Microchip Technology Inc.

4.1.3

MOVE AND ACCUMULATOR
INSTRUCTIONS

Move instructions and the DSP Accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU instruc-
tions, Move and Accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.

In summary, the following addressing modes are
supported by Move and Accumulator instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

4.1.4

MAC

INSTRUCTIONS

The dual source operand DSP instructions (

CLR,

ED,

EDAC,

MAC,

MPY,

MPY.N,

MOVSAC

and

MSC

), also

referred to as

MAC

instructions, utilize a simplified set of

addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.

The two source operand pre-fetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.

In summary, the following addressing modes are
supported by the

MAC

class of instructions:

• Register Indirect

• Register Indirect Post-modified by 2

• Register Indirect Post-modified by 4

• Register Indirect Post-modified by 6

• Register Indirect with Register Offset (Indexed)

4.1.5

OTHER INSTRUCTIONS

Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example,

BRA

(branch) instructions use 16-bit

signed literals to specify the branch destination directly,
whereas the

DISI

instruction uses a 14-bit unsigned

literal field. In some instructions, such as

ADD

Acc

, the

source of an operand or result is implied by the opcode
itself. Certain operations, such as

NOP

, do not have any

operands.

4.2

Modulo Addressing

Modulo addressing is a method of providing an auto-
mated means to support circular data buffers using
hardware. The objective is to remove the need for soft-
ware to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.

Modulo addressing can operate in either data or pro-
gram space (since the data pointer mechanism is essen-
tially the same for both). One circular buffer can be
supported in each of the X (which also provides the
pointers into Program space) and Y data spaces. Mod-
ulo addressing can operate on any W register pointer.
However, it is not advisable to use W14 or W15 for Mod-
ulo addressing, since these two registers are used as
the Stack Frame Pointer and Stack Pointer, respectively.

In general, any particular circular buffer can only be
configured to operate in one direction, as there are cer-
tain restrictions on the buffer start address (for incre-
menting buffers) or end address (for decrementing
buffers) based upon the direction of the buffer.

The only exception to the usage restrictions is for buff-
ers which have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bi-directional mode, (i.e., address bound-
ary checks will be performed on both the lower and
upper address boundaries).

Note:

For the

MOV

instructions, the addressing

mode specified in the instruction can differ
for the source and destination EA. How-
ever, the 4-bit Wb (Register Offset) field is
shared between both source and
destination (but typically only used by
one).

Note:

Not all instructions support all the address-
ing modes given above. Individual
instructions may support different subsets
of these addressing modes.

Note: