Microchip Technology dsPIC30F6010 Datasheet Download

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dsPIC30F6010

DS70119B-page 34

Advance Information

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2004 Microchip Technology Inc.

4.2.3

MODULO ADDRESSING
APPLICABILITY

Modulo addressing can be applied to the effective
address (EA) calculation associated with any W regis-
ter. It is important to realize that the address bound-
aries check for addresses less than or greater than the
upper (for incrementing buffers) and lower (for decre-
menting buffers) boundary addresses (not just equal
to). Address changes may, therefore, jump beyond
boundaries and still be adjusted correctly.

4.3

Bit-Reversed Addressing

Bit-Reversed addressing is intended to simplify data re-
ordering for radix-2 FFT algorithms. It is supported by
the X AGU for data writes only.

The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.

4.3.1

BIT-REVERSED ADDRESSING
IMPLEMENTATION

Bit-Reversed addressing is enabled when:

BWM (W register selection) in the MODCON
register is any value other than 15 (the stack can
not be accessed using bit-reversed addressing)

and

the BREN bit is set in the XBREV register

and

the addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.

If the length of a bit-reversed buffer is M = 2

bytes,

then the last ’N’ bits of the data buffer start address
must be zeros.

XB<14:0> is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.

When enabled, bit-reversed addressing will only be
executed for register indirect with pre-increment or
post-increment addressing and word sized data writes.
It will not function for any other addressing mode or for
byte-sized data, and normal addresses will be gener-
ated instead. When bit-reversed addressing is active,
the W address pointer will always be added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode will be ignored.
In addition, as word sized data is a requirement, the LS
bit of the EA is ignored (and always clear).

If bit-reversed addressing has already been enabled by
setting the BREN (XBREV<15>) bit, then a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.

FIGURE 4-2:

BIT-REVERSED ADDRESS EXAMPLE

Note:

The modulo corrected effective address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the Effective Address.
When an address offset (e.g., [W7+W2]) is
used, modulo address correction is per-
formed, but the contents of the register
remains unchanged.

Note:

All Bit-Reversed EA calculations assume
word sized data (LS bit of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.

Note:

Modulo addressing and bit-reversed
addressing should not be enabled
together. In the event that the user
attempts to do this, bit reversed address-
ing will assume priority when active for the
X WAGU, and X WAGU modulo address-
ing will be disabled. However, modulo
addressing will continue to function in the
X RAGU.

b3 b2 b1 0

b2 b3 b4 0

Bit Locations Swapped Left-to-Right
Around Center of Binary Value

Bit-Reversed Address

XB =

0x0008

for a 16-word Bit-Reversed Buffer

b7 b6 b5 b1

b7 b6 b5 b4

b11 b10 b9 b8

b15 b14 b13 b12

Sequential Address