Board Configuration
2015 Microchip Technology Inc.
DS50002403A-page 15
3.1
EXTERNAL PHY CONNECTION MODE
shows the principle connection between ESC and PHY. The clock source of
Ethernet PHYs and ESC has to be the same quartz or quartz oscillator. TX_CLK is usu-
ally not connected unless automatic TX Shift compensation is used, because the ESCs
do not incorporate a TX FIFO. The TX signals can be delayed inside the ESC for TX_-
CLK phase shift compensation. LINK_STATUS is an LED output indicating a 100 Mbit/s
(Full Duplex) link.
FIGURE 3-2:
EXTERNAL PHY CONNECTION
3.2
JUMPER SETTINGS
The default jumper settings for the LAN9252 are given below in
TABLE 3-1:
DEFAULT JUMPER SETTINGS
Jumper
Pin Settings
J4 & J7
2-3
J5 & J8
1-2
J6 & J9
1-2
J15 & J16
2-3
J19,J20,J21,J22 & J23
OPEN