Fabric DDR Subsystem
Microsemi ProprietaryUG0446 User Guide Revision 7.0
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Other activities are not performed by the controller for the duration of t
ZQinit
and t
ZQCS
. All DRAM banks
are precharged and t
RP
met before ZQCL or ZQCS commands are issued by the DDR controller.
4.6.2.1
DRAM Training
High Speed DDR3 memories typically requires the DDR controller to implement Write-Leveling, Read
DQS Gate Training, and Read Data Eye Training. However, FDDR only supports a maximum data rate of
333 MHz/667 Mbps, which means the clock period and data window are relatively large compared to
high-speed DDR3 memory interfaces. Therefore dynamic write-leveling and read training are not
performed. The following sections describe how write-leveling and read training are addressed by the
FDDR.
4.6.2.1.1
Write Leveling
Dynamic write-leveling is not required for the FDDR controller. The board-layout needs to follow AC393
SmartFusion2 and IGLOO2 Board Design Guidelines Application Note to keep the skew between DQS
and CK within the JEDEC DDR3 tDQSS limit of +/- 750ps at each memory device. For board layouts
which do not meet the Board Design Guidelines, the FDDR controller allows static delay ratios which
delays DQS for each byte lane so that the skew between DQS and CK is kept within JEDEC limits.
4.6.2.1.2
Read Leveling
FDDR does not perform dynamic Read DQS Gate Training and Data Eye Training. Instead, these
functions are achieved by using built-in static delay values automatically generated by Libero SoC for the
FDDR automatic register initialization.
5.
Read Gate
The DQS gate is aligned by the Libero SoC auto-generated FDDR initialization code containing fixed
delay ratios to account for board round-trip time between FPGA and the DDR3 memory. The
TMATCH_OUT and TMATCH_IN signals are shorted close to the FPGA balls to remove the FPGA
output and input delays from the round trip delay time. Therefore, the fixed delay ratios represent only the
board delay.
The fixed delay ratios work in combination with board layouts which follow the SmartFusion2/IGLOO2
Board Design Guidelines (refer
AC393: Board Design Guidelines for SmartFusion2/IGLOO2 FPGA
).
4.6.2.1.3
DQS Alignment within Data Eye
The incoming read DQS is internally centered within the read DQ data window using a static delay ratio.
This static delay is applied by the Libero SoC auto-generated FDDR initialization code. The fixed delay
ratios work in combination with board layouts which follow the SmartFusion2/IGLOO2 Board Design
Guidelines (refer
AC393: Board Design Guidelines for SmartFusion2/IGLOO2 FPGA Application Note
4.6.2.2
DDR Memory Initialization Time
The time to initialize the DDR memory depends on the following factors:
•
Power-up and register initialization by system controller. It depends on the power on reset delay
configuration in the Libero project (
Project > Project Settings >
Device settings
).
•
DDR controller and PHY configuration registers initialization. In SmartFusion2 devices, the Cortex-
M3 initializes these registers. In IGLOO2 devices, the ConfigMaster in the FPGA fabric initializes
these registers.
•
DDR memory initialization by the DDR Controller according to the JEDEC standard (mode register
configuration and training).
•
DDR memory settling time configured in the System Builder memory configuration window.
4.6.3
Details of Operation
This section provides a functional description of each block in the FDDR subsystem, as shown in
4.6.3.1
Clock Controller
The FDDR subsystem has a dedicated clock controller for generating aligned clocks to all the FDDR
sub-blocks for correct operation and synchronous communication with user logic in the FPGA fabric. The
