2015 Microchip Technology Inc.
Advance Information
DS50002410A-page 13
MRF24WN0MA/MB
2.4
Interrupt Pin
The SPI_INT line works in conjunction with the SPI
port. It is an active-low output signal to the host MCU to
signal an interrupt event.
2.5
VDD and GND Pin
The MRF24WN0MA/MB wireless module contains an
integrated power management unit that generates all
necessary voltages required by the internal circuitry.
The module is powered from a single voltage source.
Table 2-3
lists the recommended bypass capacitors.
The capacitors must be closely placed to the module.
2.6
Hibernate
The module enters the lowest power mode when the
HIBERNATE pin is asserted low. No state information
is preserved. The MPLAB Harmony framework can
save state information in the host MCU that can be
restored after wake-up (HIBERNATE pin is asserted
high).
The module can wake-up when HIBERNATE pin is
asserted high. The module must be initialized and any
state information saved prior to Hibernate state is
restored. This process approximately takes 40 ms.
TABLE 2-3:
RECOMMENDED BYPASS
CAPACITORS
Pin
Symbol
Bypass Capacitors
4
VDD
0.1 µF and 2.2 µF
15
VDD
0.1 µF and 2.2 µF
35
VDD
0.1 µF and 2.2 µF
Summary of Contents for MRF24WN0MA
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