2003 Microchip Technology Inc.
DS39582B-page 183
PIC16F87XA
FIGURE 17-5:
CLKO AND I/O TIMING
TABLE 17-4:
CLKO AND I/O TIMING REQUIREMENTS
Note: Refer to Figure 17-3 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4
Q1
Q2
Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value
New Value
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units Conditions
10*
T
OS
H2
CK
L OSC1
↑
to CLKO
↓
—
75
200
ns
(Note 1)
11*
T
OS
H2
CK
H OSC1
↑
to CLKO
↑
—
75
200
ns
(Note 1)
12*
T
CK
R
CLKO Rise Time
—
35
100
ns
(Note 1)
13*
T
CK
F
CLKO Fall Time
—
35
100
ns
(Note 1)
14*
T
CK
L2
IO
V
CLKO
↓
to Port Out Valid
—
—
0.5 T
CY
+ 20
ns
(Note 1)
15*
T
IO
V2
CK
H
Port In Valid before CLKO
↑
T
OSC
+ 200
—
—
ns
(Note 1)
16*
T
CK
H2
IO
I
Port In Hold after CLKO
↑
0
—
—
ns
(Note 1)
17*
T
OS
H2
IO
V
OSC1
↑
(Q1 cycle) to Port Out Valid
—
100
255
ns
18*
T
OS
H2
IO
I
OSC1
↑
(Q2 cycle) to Port Input
Invalid (I/O in hold time)
Standard (F)
100
—
—
ns
Extended (LF)
200
—
—
ns
19*
T
IO
V2
OS
H Port Input Valid to OSC1
↑
(I/O in setup time)
0
—
—
ns
20*
T
IO
R
Port Output Rise Time
Standard (F)
—
10
40
ns
Extended (LF)
—
—
145
ns
21*
T
IO
F
Port Output Fall Time
Standard (F)
—
10
40
ns
Extended (LF)
—
—
145
ns
22††*
T
INP
INT pin High or Low Time
T
CY
—
—
ns
23††*
T
RBP
RB7:RB4 Change INT High or Low Time
T
CY
—
—
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
††
These parameters are asynchronous events not related to any internal clock edges.
Note
1:
Measurements are taken in RC mode where CLKO output is 4 x T
OSC
.
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