PIC16F87XA
DS39582B-page 190
2003 Microchip Technology Inc.
TABLE 17-9:
SPI MODE REQUIREMENTS
FIGURE 17-15:
I
2
C BUS START/STOP BITS TIMING
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
70*
T
SS
L2
SC
H,
T
SS
L2
SC
L
SS
↓
to SCK
↓
or SCK
↑
Input
T
CY
—
—
ns
71*
T
SC
H
SCK Input High Time (Slave mode)
T
CY
+ 20
—
—
ns
72*
T
SC
L
SCK Input Low Time (Slave mode)
T
CY
+ 20
—
—
ns
73*
T
DI
V2
SC
H,
T
DI
V2
SC
L
Setup Time of SDI Data Input to SCK Edge
100
—
—
ns
74*
T
SC
H2
DI
L,
T
SC
L2
DI
L
Hold Time of SDI Data Input to SCK Edge
100
—
—
ns
75*
T
DO
R
SDO Data Output Rise Time
Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
76*
T
DO
F
SDO Data Output Fall Time
—
10
25
ns
77*
T
SS
H2
DO
Z
SS
↑
to SDO Output High-Impedance
10
—
50
ns
78*
T
SC
R
SCK Output Rise Time
(Master mode)
Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
79*
T
SC
F
SCK Output Fall Time (Master mode)
—
10
25
ns
80*
T
SC
H2
DO
V,
T
SC
L2
DO
V
SDO Data Output Valid after
SCK Edge
Standard(F)
Extended(LF)
—
—
—
—
50
145
ns
81*
T
DO
V2
SC
H,
T
DO
V2
SC
L
SDO Data Output Setup to SCK Edge
T
CY
—
—
ns
82*
T
SS
L2
DO
V
SDO Data Output Valid after SS
↓
Edge
—
—
50
ns
83*
T
SC
H2
SS
H,
T
SC
L2
SS
H
SS
↑
after SCK Edge
1.5 T
CY
+ 40
—
—
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note: Refer to Figure 17-3 for load conditions.
91
93
SCL
SDA
Start
Condition
Stop
Condition
90
92
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