2003 Microchip Technology Inc.
DS39582B-page 193
PIC16F87XA
FIGURE 17-17:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 17-18:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 17-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Note: Refer to Figure 17-3 for load conditions.
121
121
122
RC6/TX/CK
RC7/RX/DT
pin
pin
120
Param
No.
Symbol
Characteristic
Min
Typ†
Max Units Conditions
120
T
CK
H2
DT
V SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
Standard(F)
—
—
80
ns
Extended(LF)
—
—
100
ns
121
T
CKRF
Clock Out Rise Time and Fall Time
(Master mode)
Standard(F)
—
—
45
ns
Extended(LF)
—
—
50
ns
122
T
DTRF
Data Out Rise Time and Fall Time
Standard(F)
—
—
45
ns
Extended(LF)
—
—
50
ns
† Data in “Typ” column is at 5V, 25
°
C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note: Refer to Figure 17-3 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
125
T
DT
V2
CK
L
SYNC RCV (MASTER & SLAVE)
Data Setup before CK
↓
(DT setup time)
15
—
—
ns
126
T
CK
L2
DTL
Data Hold after CK
↓
(DT hold time)
15
—
—
ns
† Data in “Typ” column is at 5V, 25
°
C unless otherwise stated. These parameters are for design guidance
only and are not tested.
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