PIC16F87XA
DS39582B-page 34
2003 Microchip Technology Inc.
REGISTER 3-1:
EECON1 REGISTER (ADDRESS 18Ch)
R/W-x
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
—
—
—
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Program/Data EEPROM Select bit
1
= Accesses program memory
0
= Accesses data memory
Reads ‘
0
’ after a POR; this bit cannot be changed while a write operation is in progress.
bit 6-4
Unimplemented: Read as ‘
0
’
bit 3
WRERR: EEPROM Error Flag bit
1
= A write operation is prematurely terminated (any MCLR or any WDT Reset during normal
operation)
0
= The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1
= Allows write cycles
0
= Inhibits write to the EEPROM
bit 1
WR: Write Control bit
1
= Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0
= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1
= Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0
= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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