2003 Microchip Technology Inc.
DS39582B-page 89
PIC16F87XA
FIGURE 9-11:
I
2
C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSP
IF
BF (
SS
PST
A
T
<
0
>)
S
1
2
3
4
56
7
8
9
1
23
4
5
6
7
89
1
2
3
4
5
7
8
9
P
1
1
11
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
11
1
0
A
8
R/W=
1
AC
K
AC
K
R/W
=
0
ACK
R
e
ceive F
ir
s
t B
y
te of
A
d
d
ress
Cle
a
re
d
in
so
ft
wa
re
B
u
s m
a
ster
term
inates
tran
sfer
A9
6
(P
IR
1<
3>
)
R
e
ce
iv
e
S
e
cond B
y
te
of A
ddre
s
s
C
lear
ed by
hard
w
are w
h
en
S
S
P
A
D
D
i
s
u
pdate
d
w
it
h l
o
w
byte
of ad
dress
UA (
S
S
PST
A
T
<1
>)
Clo
ck is h
e
ld
lo
w u
n
til
up
date o
f S
S
P
A
D
D
ha
s
ta
ken
pl
ace
UA
is se
t indicatin
g
that
the S
S
P
A
D
D
need
s to be
upda
ted
U
A
i
s
set
i
ndi
cati
ng
that
S
S
P
A
D
D
need
s to be
u
pdate
d
C
lea
red b
y
har
dw
are
w
hen
S
S
P
A
D
D
i
s
upda
ted w
it
h h
igh
b
y
te of a
ddre
s
s
SS
PBUF
is wr
it
te
n
with
cont
ent
s of S
S
P
S
R
D
umm
y re
ad of S
S
P
B
U
F
to cle
a
r B
F
f
la
g
R
e
cei
v
e F
irst B
y
te
of A
ddre
s
s
12
3
4
5
7
8
9
D
7
D6
D5
D4
D3
D
1
AC
K
D2
6
T
ran
smitting D
a
ta
B
y
te
D0
D
umm
y re
ad of
S
S
P
B
U
F
to cle
a
r B
F
f
la
g
Sr
Cle
a
re
d
in
so
ftwa
re
W
rit
e
o
f SS
PBUF
in
itia
te
s tr
a
n
sm
it
C
lea
re
d i
n
s
o
ft
w
a
re
Co
m
p
le
tio
n
o
f
cl
ear
s B
F
fl
ag
C
KP (
SSP
CO
N<4
>
)
CK
P
is set in
software
C
K
P
i
s
aut
omati
c
a
lly
cl
e
ared
i
n har
dw
are
hol
di
ng
S
C
L
l
ow
Clo
ck is h
e
ld
lo
w u
n
til
upd
ate of
S
S
P
A
D
D
has
ta
ken p
lace
da
ta
tran
smi
ssi
on
Clo
ck is h
e
ld
lo
w u
n
til
CK
P
is set to
‘
1
’
B
F
f
la
g
is clear
th
ir
d ad
dress s
equen
ce
at
the e
nd of t
h
e
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