2003 Microchip Technology Inc.
DS39582B-page 91
PIC16F87XA
9.4.4.5
Clock Synchronization and the
CKP Bit
When the CKP bit is cleared, the SCL output is forced
to ‘
0
’; however, setting the CKP bit will not assert the
SCL output low until the SCL output is already sampled
low. Therefore, the CKP bit will not assert the SCL line
until an external I
2
C master device has already
asserted the SCL line. The SCL output will remain low
until the CKP bit is set and all other devices on the I
2
C
bus have deasserted SCL. This ensures that a write to
the CKP bit will not violate the minimum high time
requirement for SCL (see Figure 9-12).
FIGURE 9-12:
CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX-1
DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock
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